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FDMS6681Z Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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FDMS6681Z Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 7 page www.fairchildsemi.com 4 ©2009 Fairchild Semiconductor Corporation FDMS6681Z Rev.C4 Figure 7. 0 50 100 150 200 0 2 4 6 8 10 Qg, GATE CHARGE (nC) ID = -22.1 A VDD = -15 V VDD = -20 V VDD = -10 V Gate Charge Characteristics Figure 8. 0.1 1 10 600 1000 10000 20000 f = 1 MHz VGS = 0 V -VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss 30 Capacitance vs Drain to Source Voltage Figure 9. Unclamped Inductive SwitchingCapability 0.001 0.01 0.1 1 10 100 1 50 TJ = 100 oC TJ = 25 oC TJ = 125 oC t AV, TIME IN AVALANCHE (ms) 100 Figure 10. 0 5 10 15 20 25 30 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 VGS = 0 V TJ = 25 oC TJ = 150 oC VGS, GATE TO SOURCE VOLTAGE (V) Igss vs Vgss Figure 11. 0.01 0.1 1 10 100 0.01 0.1 1 10 100 10 s 1 s DC 100 ms 10 ms 1 ms -VDS, DRAIN to SOURCE VOLTAGE (V) THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE TJ = MAX RATED R JA = 125 oC/W TA = 25 oC Forward Bias Safe Operating Area Figure 12. 0.001 0.01 0.1 1 10 100 1000 0.1 1 10 100 1000 SINGLE PULSE R JA = 125 oC/W TA = 25 oC V GS = -10 V t, PULSE WIDTH (sec) Single Pulse Maximum Power Dissipation Typical Characteristics T J = 25 °C unless otherwise noted |
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