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XR16M598IQ100 Datasheet(PDF) 8 Page - Exar Corporation |
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XR16M598IQ100 Datasheet(HTML) 8 Page - Exar Corporation |
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8 / 58 page  XR16M598 8 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 16-BYTE FIFO REV. 1.0.0 2.3 Simultaneous Write to All Channels During a write cycle, the setting of the Device Configuration register REGB (See Table 9) bit-0 to a logic 1 will override the channel selection of address A6:A4 and allow a simultaneous write to all 8 UART channels when any channel is written to. This functional capability allow the registers in all 8 UART channels to be modified concurrently, saving individual channel initialization time. Caution should be considered, however, when using this capability. Any in-process serial data transfer may be disrupted by changing an active channel’s mode. 2.4 INT# Ouput The INT# interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. TABLE 3: INT# PIN OPERATION FOR TRANSMITTER Auto RS485 Mode FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) NO HIGH = a byte in THR LOW = THR empty HIGH = FIFO above trigger level LOW = FIFO below trigger level or FIFO empty YES HIGH = a byte in THR LOW = transmitter empty HIGH = FIFO above trigger level LOW = FIFO below trigger level or transmitter empty TABLE 4: INT# PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) HIGH = no data LOW = 1 byte HIGH = FIFO below trigger level LOW = FIFO above trigger level |
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