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XR16M580IB25 Datasheet(PDF) 7 Page - Exar Corporation |
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XR16M580IB25 Datasheet(HTML) 7 Page - Exar Corporation |
7 / 56 page XR16M580 7 REV. 1.0.0 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The M580 data interface supports the Intel and motorola compatible types of CPUs. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is shown in Figure 4. FIGURE 4. XR16M580 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS VCC VCC A0 A1 A2 UART_CS# IOR# IOW# CS# IOR# IOW# UART_INT INT Intel Data Bus Interconnections GND UART_RESET RESET 16/68# RI# CD# DSR# CTS# RTS# DTR# RX TX PwrSave D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 Serial Transceivers of RS-232 RS-485 RS-422 Or Infrared POWERSAVE VCC VCC A0 A1 A2 UART_CS# R/W# D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 CS# D0 D1 D2 D3 D4 D5 D6 D7 IOR# IOW# UART_IRQ# INT Motorola Data Bus Interconnections GND UART_RESET# RESET RI# CD# DSR# CTS# RTS# DTR# RX TX NC 16/68# vcc POWERSAVE PwrSave Serial Transceivers of RS-232 RS-485 RS-422 Or Infrared |
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