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XRT91L31 Datasheet(PDF) 7 Page - Exar Corporation |
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XRT91L31 Datasheet(HTML) 7 Page - Exar Corporation |
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7 / 41 page  XRT91L31 7 REV. 1.0.2 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER CDRREFSEL LVTTL, LVCMOS I 60 Clock and Data Recover Unit Reference Frequency Select Selects the Clock and Data Recovery Unit reference frequency based on the table below. "Low" = CDR uses CMU’s reference clock "High" = CDR reference clock from CDRAUXREF- CLK NOTE: CDRAUXREFCLK requires accuracy of 77.76 MHz ppm. LOOPTIME LVTTL, LVCMOS I 2 Loop Timing Mode When the loop timing mode is activated the external reference clock to the input of the Retimer is replaced with the high-speed recovered receive clock from the CDR. "Low" = Disabled "High" = Loop timing Activated CDRDIS LVTTL, LVCMOS I 12 Clock and Data Recovery Unit Disable Active "High." Disables internal Clock and Data Recovery unit. Received serial data bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of externally recovered differential clock XRXCLKIP/N coming from the opti- cal module. "Low" = Internal CDR unit is Enabled "High" = Internal CDR unit is Disabled and Bypassed PIN DESCRIPTION NAME LEVEL TYPE PIN DESCRIPTION CDRREF- SEL STS12/ STS3 CDRAUXREF- CLK Frequency Data Rate 0 CDR uses CMU’s reference clock (see CMUFREQSEL pin) 1 0 77.76 MHz STS-3/STM-1 155.52 Mbps 1 1 77.76 MHz STS-12/STM-4 622.08 Mbps 200 +− |
Similar Part No. - XRT91L31 |
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Similar Description - XRT91L31 |
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