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ADM12914-2ARQZ-RL7 Datasheet(PDF) 5 Page - Analog Devices |
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ADM12914-2ARQZ-RL7 Datasheet(HTML) 5 Page - Analog Devices |
5 / 16 page ADM12914 Rev. 0 | Page 5 of 16 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VH1 1 VL1 2 VH2 3 VL2 4 VCC 16 TIMER 15 SEL 14 LATCH 13 VH3 5 VL3 6 VH4 7 UV 12 OV 11 REF 10 VL4 8 GND 9 ADM12914-1 TOP VIEW (Not to Scale) Figure 2. ADM12914-1 Pin Configuration VCC 16 VH1 1 VL1 2 TIMER 15 VH2 3 SEL 14 VL2 4 DIS 13 VH3 5 UV 12 VL3 6 OV 11 VH4 7 REF 10 GND 9 ADM12914-2 TOP VIEW (Not to Scale) VL4 8 Figure 3. ADM12914-2 Pin Configuration Table 4. Pin Function Descriptions Pin No. ADM12914-1 ADM12914-2 Mnemonic Description 1, 3 1, 3 VH1, VH2 Voltage High Input 1 and Voltage High Input 2. If the voltage monitored by VH1 or VH2 drops below 0.5 V an undervoltage condition is detected. Connect to VCC when not in use. 2, 4 2, 4 VL1, VL2 Voltage Low Input 1. If the voltage monitored by VL1 or VL2 rises above 0.5 V an overvoltage condition is detected. Tie to GND when not in use. 5, 7 5, 7 VH3, VH4 Voltage High Input 3 and Voltage High Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VH3 and VH4 drops below 0.5 V, an undervoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input drops below 0.5 V, an overvoltage condition is detected. Connect to VCC when not in use. 6, 8 6, 8 VL3, VL4 Voltage Low Input 3 and Voltage Low Input 4. The polarity of these inputs is determined by the state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage and the voltage monitored by VL3 or VL4 rises above 0.5 V, an overvoltage condition is detected. Conversely, when the input is configured as a negative voltage and the input rises above 0.5 V, an undervoltage condition is detected. Tie to GND when not in use. 9 9 GND Device Ground. 10 10 REF Buffered Reference Output. This pin is a 1 V reference that is used as an offset when monitoring negative voltages. This pin can source or sink 1 mA, and drive loads up to 1 nF. Larger capacitive loads may lead to instability. Leave unconnected when not in use. 11 11 OV Overvoltage Reset Output. OV is asserted low if a negative polarity input voltage drops below its associated threshold or if a positive polarity input voltage exceeds its threshold. The ADM12914-1 allows OV to be latched low. The ADM12914-2 holds OV low for an adjustable timeout period determined by the timer capacitor. This pin has a weak pull-up to VCC and can be pulled up to 16 V externally. Leave this pin unconnected when not in use 12 12 UV Undervoltage Reset Output. UV is asserted low if a negative polarity input voltage exceeds its associated threshold or if a positive polarity input voltage drops below its threshold. UV is held low for an adjustable timeout period set by the external capacitor tied to the TIMER pin. The UV pin has a weak pull-up to VCC and can be pulled up to 16 V externally via an external pull-up resistor. Leave this pin unconnected when not in use. 13 N/A1 LATCH OV Latch Bypass Input/Clear Pin. When pulled high, the OV latch is cleared. When held high, the OV output has the same delay and output characteristics as the UV output. When pulled low, the OV output is latched when asserted. (Applies only to the ADM12914-1.) N/A1 13 DIS OV and UV Disable Input. When pulled high, the OV and UV outputs are held high irrespective of the state of the VHx and VLx input pins. However, if a UVLO condition occurs, the OV and UV outputs are asserted. This pin has a weak internal pull-down (2 μA) to GND. Leave this pin unconnected when not in use. (Applies only to the ADM12914-2.) 14 14 SEL Input Polarity Select. This three-state input pin allows the polarity of VH3, VL3, VH4, and VL4 to be configured. Connect this pin to VCC or GND, or leave it open to select one of three possible input polarity configurations (see Table 5). |
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