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AD9572ACPZPEC-R7 Datasheet(PDF) 6 Page - Analog Devices |
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AD9572ACPZPEC-R7 Datasheet(HTML) 6 Page - Analog Devices |
6 / 20 page AD9572 Rev. 0 | Page 6 of 20 CLOCK OUTPUTS Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. Table 6. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL CLOCK OUTPUTS Output Frequency 156.25 MHz Output High Voltage (VOH) VS − 1.24 VS − 1.05 VS − 0.83 V Output Low Voltage (VOL) VS − 2.07 VS − 1.87 VS − 1.62 V Output Differential Voltage (VOD) 700 825 950 mV Duty Cycle 45 55 % LVDS CLOCK OUTPUTS Output Frequency 156.25 MHz Differential Output Voltage (VOD) 250 350 475 mV Delta VOD 25 mV Output Offset Voltage (VOS) 1.125 1.25 1.375 V Delta VOS 25 mV Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND Duty Cycle 45 55 % CMOS CLOCK OUTPUTS Output Frequency 33.33 MHz Output High Voltage (VOH) VS − 0.1 V Sourcing 1.0 mA current Output Low Voltage (VOL) 0.1 V Sinking 1.0 mA current Duty Cycle 42 58 % TIMING CHARACTERISTICS Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. Table 7. Parameter Min Typ Max Unit Test Conditions/Comments LVPECL Termination = 200 Ω to 0 V; CLOAD = 0 pF Output Rise Time, tRP 480 625 810 ps 20% to 80%, measured differentially Output Fall Time, tFP 480 625 810 ps 80% to 20%, measured differentially LVDS Termination = 100 Ω differential; CLOAD = 0 pF Output Rise Time, tRL 160 350 540 ps 20% to 80%, measured differentially Output Fall Time, tFL 160 350 540 ps 80% to 20%, measured differentially CMOS Termination = 50 Ω to 0 V; CLOAD = 5 pF Output Rise Time, tRC 0.25 0.50 2.5 ns 20% to 80% Output Fall Time, tFC 0.25 0.70 2.5 ns 80% to 20% |
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