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SMJ44C251B10SVM Datasheet(PDF) 4 Page - Austin Semiconductor |
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SMJ44C251B10SVM Datasheet(HTML) 4 Page - Austin Semiconductor |
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4 / 57 page  VRAM VRAM VRAM VRAM VRAM SMJ44C251B MT42C4256 Austin Semiconductor, Inc. SMJ44C251B/MT42C4256 Rev. 0.1 12/03 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 4 FUNCTION TABLE CAS\ FALL CAS\ TRG\ W\ 1 DSF SE\ DSF RAS\ CAS\ RAS\ CAS\ 2 W\ CBR Refresh L XXXXX X X XX R Register-to-memory transfer (transfer write) H L LXLX Row Addr Tap Point XX T Alternate transfer write (independent of SE\) HL LH X X Row Addr Tap Point XX T Serial-write-mode enable (pseudo-transfer write) H LLL H X Refresh Addr Tap Point XX T Memory-to-register transfer (transfer read) HLHL X X Row Addr Tap Point XX T Split-register-transfer read (must reload tap) HLH H X X Row Addr Tap Point XX T Load and use write mask, Write data to DRAM H LLL X L Row Addr Col Addr DQ Mask Valid Data R Load and use write mask, Block write to DRAM HH L L X H Row Addr Blk Addr A2-A8 DQ Mask Col Mask R Persistent write-per-bit, Write data to DRAM HH L H X L Row Addr Col Addr X Valid Data R Persistent write-per-bit, Block write to DRAM HH L H X H Row Addr Blk Addr A2-A8 X Col Mask R Normal DRAM read/write (nonmasked) HHH L X L Row Addr Col Addr X Valid Data R Block write to DRAM (nonmasked) HHH L X H Row Addr Blk Addr A2-A8 X Col Mask R Load write mask HHHH X L Refresh Addr XX DQ Mask R Load color register HHHH X H Refresh Addr XX Color Data R RAS\ FALL FUNCTION ADDRESS TYPE 3 DQ0 - DQ3 NOTES: 1. In persistent write-per-bit function, W\ must be high during the refresh cycle. 2. DQ0 - DQ3 are latched on the later of W\ or CAS\ falling edge. Col Mask = H: Write to address/column location enabled. DQ Mask = H: Write to I/O enabled. 3. R = random access operation, T = transfer operation. LEGEND H = HIGH L = LOW X = Don’t Care |
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