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SMJ44C251B12JDM Datasheet(PDF) 7 Page - Austin Semiconductor

Part # SMJ44C251B12JDM
Description  256K X 4 VRAM 256K x 4 DRAM with 512K x 4 SAM
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Manufacturer  AUSTIN [Austin Semiconductor]
Direct Link  http://www.austinsemiconductor.com
Logo AUSTIN - Austin Semiconductor

SMJ44C251B12JDM Datasheet(HTML) 7 Page - Austin Semiconductor

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VRAM
VRAM
VRAM
VRAM
VRAM
SMJ44C251B
MT42C4256
Austin Semiconductor, Inc.
SMJ44C251B/MT42C4256
Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
RANDOM-ACCESS-OPERATION FUNCTIONS
CAS\
FALL
CAS\
TRG\
W\
1
DSF
SE\
DSF
RAS\
CAS\
RAS\ CAS\
2
W\
CBR Refresh
L
XXXXX
X
X
XX
Load and use write mask,
Write data to DRAM
HH
L
L
X
L
Row
Addr
Col
Addr
DQ
Mask
Valid
Data
Load and use write mask,
Block write to DRAM
HH
L
L
X
H
Row
Addr
Blk Addr
A2-A8
DQ
Mask
Col
Mask
Persistent write-per-bit,
Write data to DRAM
HH
L
H
X
L
Row
Addr
Col
Addr
X
Valid
Data
Persistent write-per-bit,
Block write to DRAM
HH
L
H
X
H
Row
Addr
Blk Addr
A2-A8
X
Col
Mask
Normal DRAM read/write
(nonmasked)
HHH
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Block write to DRAM
(nonmasked)
HHH
L
X
H
Row
Addr
Blk Addr
A2-A8
X
Col
Mask
Load write mask
HHHH
X
L
Refresh
Addr
XX
DQ
Mask
Load color register
HHHH
X
H
Refresh
Addr
XX
Color
Data
RAS\ FALL
FUNCTION
ADDRESS
DQ0 - DQ3
NOTES:
1. In persistent write-per-bit function, W must be high during the refresh cycle.
2. DQ0–DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled.
DQ Mask = H: Write to I/O enabled
LEGEND:
H = High
L = Low
X = Don’t care
RANDOM-ACCESS OPERATION
The random-access operation functions are summarized in
the “Random-Access-Operation Function” table and described
in the following sections.
ENHANCED PAGE-MODE
Enhanced page-mode operation allows faster memory
access by keeping the same row address while selecting
random column addresses. This mode eliminates the time
required for row address setup-and-hold and address
multiplex. The maximum RAS\ low time and the CAS\ page cycle
time used determine the number of columns that can be
accessed.
Unlike conventional page-mode operation, the enhanced
page mode allows the SMJ44C251B/MT42C4256 to operate at a
higher data bandwidth. Data retrieval begins as soon as the
column address is valid rather than when CAS\ transitions low.
A valid column address can be presented immediately after
row-address hold time has been satisfied, usually well in ad-
vance of the falling edge of CAS\. In this case, data can be
obtained after t
a(C)
max (access time from CAS low), if t
a(CA)
max
(access time from column address) has been satisfied.
REFRESH
There are three types of refresh available on the
SMJ44C251B/MT42C4256: RAS\-only refresh, CBR refresh, and
hidden refresh.
RAS\-ONLY REFRESH
A refresh operation must be performed to each row at least
once every 8 ms to retain data. Unless CAS\ is applied, the
output buffers are in the high-impedance state, so the RAS\-
only refresh sequence avoids any output during refresh. Exter-
nally generated addresses must be supplied during RAS-only
refresh. Strobing each of the 512 row addresses with RAS causes
(continued)


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