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SMX55161A-70HKCM Datasheet(PDF) 9 Page - Austin Semiconductor |
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SMX55161A-70HKCM Datasheet(HTML) 9 Page - Austin Semiconductor |
9 / 64 page VRAM SM55161A Production Austin Semiconductor, Inc. AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice. 9 SMJ55161A Rev. 1.6 03/05 enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting ran- dom column addresses. This mode eliminates the time required for row-address setup, row-address hold, and address multi- plex. The maximum RAS\ low time and CAS\ page cycle time used determine the number of columns that can be accessed. Unlike conventional page-mode operations, the enhanced page mode allows the SMJ55161A to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CASx\ transitions low. A valid column address can be presented immediately after the row-address hold time has been satisfied, usually well in advance of the falling edge of CASx\. In this case, data is obtained after t a(C) MAX (access time from CASx\ low) if t a(CA) MAX (access time from column address) has been satisfied. REFRESH CAS-before-RAS (CBR) refresh CBR refreshes are accomplished by bringing either or both CASL\ and CASU\ low earlier than RAS\. The external row address is ignored, and the refresh row address is generated internally. Three types of CBR refresh cycles are available. The CBR refresh (option reset) ends the persistent write-per-bit mode and the stop-point mode. The CBRN and CBRS refreshes (no reset) do not end the persistent write-per-bit mode or the stop- point mode. The 512 rows of the DRAM do not necessarily need to be refreshed consecutively as long as the entire refresh is completed within the required time period, t rf(MA) . The output buffers remain in the high-impedance state during the CBR refresh cycles regardless of the state of TRG\. hidden refresh A hidden refresh is accomplished by holding both CASL\ and CASU\ low in the DRAM read cycle and cycling RAS\. The output data of the DRAM read cycle remains valid while the refresh is carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh. RAS-only refresh A RAS\-only refresh is accomplished by cycling RAS\ at every row address. Unless CASx\ and TRG\ are low, the output buffers remain in the high-impedance state to conserve power. Externally-generated addresses must be supplied during RAS\- only refresh. Strobing each of the 512 row addresses with RAS\ causes all bits in each row to be refreshed. extended data output The SMJ55161A features EDO during DRAM accesses. While RAS\ and TRG\ are low, the DRAM output remains valid. The output remains valid even when CASx\ returns high until WE\ is low, TRG\ is high, or both CASx\ and RAS\ are high (see Figure 1 and Figure 2). The EDO mode functions during all read cycles including DRAM read, page-mode read, and read- modify-write cycles (see Figure 3). FIGURE 1: DRAM Read Cycle With RAS\-Controlled Output |
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