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AS28F128J3M Datasheet(PDF) 1 Page - Austin Semiconductor |
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AS28F128J3M Datasheet(HTML) 1 Page - Austin Semiconductor |
1 / 8 page AS28F128J3MRG Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification Revision 5.0 11/23/04 For Additional Products and Information visit out Web site at www.austinsemiconductor.com 1 PEM AS28F128J3M Austin Semiconductor, Inc. Q-Flash A22 CE1 A21 A18 A17 A16 VCC A10 A9 A7 A6 A5 A4 A1 A13 A12 WE\ OE\ DQ7 DQ14 DQ6 VSS DQ12 DQ4 DQ10 DQ2 DQ1 DQ8 DQ0 A0 CE2 NC STS DQ5 VCC A23 DQ15 DQ13 DQ9 BYTE\ VCCQ DQ11 VSS A20 A14 A8 A2 A19 A15 VSS A3 1 2 3 4 5 6 7 8 9 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 DQ3 28 27 26 25 24 23 CE0 RP\ VPEN A11 22 21 20 19 18 17 16 15 14 13 12 10 11 Plastic Encapsulated Microcircuit 128Mb, x8 and x16 Q-FLASH Memory Even Sectored, Single Bit per Cell Architecture Features • 100% Pin and Function compatible to Intel’s MLC Family • NOR Cell Architecture • 2.7V to 3.6V VCC • 2.7V to 3.6V or 5V VPEN (Programming Voltage) • Asynchronous Page Mode Reads • Manufacturer’s ID Code: ! MT28F128J3MRG Micron 0x2Ch • Industry Standard Pin-Out • Fully compatible TTL Input and Outputs • Common Flash Interface [CFI] • Scalable Command Set • Automatic WRITE and ERASE Algorithms • 5.6us per Byte effective programming time • 128 bit protection register ! 64-bit unique device identifier ! 64-bit user programmable OTP cells • Enhanced data protection feature with use of VPEN=VSS • Security OTP block feature • 100,000 ERASE cycles per BLOCK • Automatic Suspend Options: ! Block ERASE SUSPEND-to-READ ! Block ERASE SUSPEND-to-PROGRAM ! PROGRAM SUSPEND-to-READ • Available Operating Ranges: ! Enhanced [-ET]-40 oC to +105oC ! Mil-Temperature [-XT]-55oC to +125oC For in-depth functional product detail and Timing Diagrams, please reference Micron’s full product Datasheet: MT28F640J3 Rev. L Dated 04/16/04 General Description ASI’s, AS28F128J3M Enhanced or Mil-Temp variant of Micron’s Q-Flash family of devices, is a nonvolatile, electrically block- erasable (FLASH), programmable memory device manufactured using Micron’s 0.15um process technology. This device containing 134,217,728 bits organized as either 16,777,218 (x8) or 8,388,608 bytes (x16). The device is uniformly sectored with one hundred and twenty eight 128KB ERASE blocks. This device features in-system block locking. They also have a Common FLASH Interface [CFI] that permits software algorithms to be used for entire families of devices. The software is device- independent, JEDEC ID-independent with forward and backward compatibility. A B C D E F G H 1 23 4 5 6 78 A1 A2 A3 A4 A6 A8 A7 A5 A10 A11 A12 A13 A14 A15 VPEN CE0 VSS A9 RP\ DNU DNU DNU DNU DNU DNU DNU CE2 A18 A19 A20 A16 A17 A21 A22 CE1 VCC A25 DQ4 DQ3 DQ9 DQ1 DQ8 DQ15 STS BYTE\ DQ0 DQ10 DQ11 DQ12 OE\ A23 A0 DQ2 VCCQ DQ5 DQ6 DQ14 WE\ VSS VCC DQ13 VSS DQ7 A24 PIN ASSIGNMENT 64-Ball FBGA |
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