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AS8nvC512K32QC-45XT Datasheet(PDF) 9 Page - Austin Semiconductor |
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AS8nvC512K32QC-45XT Datasheet(HTML) 9 Page - Austin Semiconductor |
9 / 17 page AUSTIN SEMICONDUCTOR, INC. nvSRAM nvSRAM nvSRAM nvSRAM nvSRAM AS8nvC512K32 AS8nvC512K32 Rev. 0.0 08/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 9 Austin Semiconductor, Inc. ADVANCE INFORMATION AC Switching Characteristics Switching Waveforms SRAM Read Cycle #1: Address Controlled 13, 14, 17 Address Data Output Address Valid Previous Data Valid Output Data Valid t RC t AA t OHA Notes 13.WE\ must be HIGH during SRAM read cycles. 14. Device is continuously selected with CE\, OE\ LOW. 15.Measured ±200 mV from steady state output voltage. 16. If WE\ is LOW when CE\ goes LOW, the outputs remain in the high impedance state. 17. HSB\ must remain HIGH during read and write cycles. Austin Semi Parameters Alt Parameters Min Max Min Max Min Max tACE tACS Chip Enable Access Time 20 25 45 ns tRC 13 tRC Read Cycle Time 20 25 45 ns tAA 14 tAA Address Access Time 20 25 45 ns tDOE tOE Output Enable to Data Valid 10 12 20 ns tOHA 14 tOH Output Hold After Address Change 2 2 2 ns tLZCE 12, 15 tLZ Chip Enable to Output Active 2 2 2 ns tHZCE 12, 15 tHZ Chip Disable to Output Active 8 10 15 ns tLZOE 12, 15 tOLZ Output Enable to Output Active 0 0 0 ns tHZOE 12, 15 tOHZ Output Disable to Output Inactive 8 10 15 ns tPU 12 tPA Chip Enable to Power Active 0 0 0 ns tPD 12 tPS Chip Disable to Power Standby 20 25 45 ns tDBE Byte Enable to Data Valid 10 12 20 ns tLZBE 12 Byte Enable to Output Active 0 0 0 ns tHZBE 12 Byte Disable to Output Inactive 8 10 15 ns tWC tWC Write Cycle Time 20 25 45 ns tPWE tWP Write Pulse Width 15 20 30 ns tSCE tCW Chip Enable to End of Write 15 20 30 ns tSD tDW Data Setup to End of Write 8 10 15 ns tHD tDH Data Hold After End of Write 0 0 0 ns tAW tAW Address Setup to End of Write 15 20 30 ns tSA tAS Address Setup to End of Write 0 0 0 ns tHA tWR Address Hold After End of Write 0 0 0 ns tHZWE 12, 15, 16 tWZ Write Enable to Output Disable 8 10 15 ns tLZWE 12, 15 tOW Output Active after End of Write 2 2 2 ns tBW Byte Enable to End of Write 15 20 30 ns SRAM Read Cycle SRAM Write Cycle Parameters Description 20 ns 25 ns 45 ns Unit |
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