AUSTIN SEMICONDUCTOR, INC.

nvSRAM

nvSRAM

nvSRAM

nvSRAM

nvSRAM

AS8nvC512K32

AS8nvC512K32

Rev. 0.0 08/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

9

Austin Semiconductor, Inc.

ADVANCE INFORMATION

AC Switching Characteristics

Switching Waveforms

Address

Data Output

Address Valid

Previous Data Valid

Output Data Valid

t

RC

t

AA

t

OHA

Notes

13.WE\ must be HIGH during SRAM read cycles.

14. Device is continuously selected with CE\, OE\ LOW.

15.Measured ±200 mV from steady state output voltage.

16. If WE\ is LOW when CE\ goes LOW, the outputs remain in the high impedance state.

17. HSB\ must remain HIGH during read and write cycles.

Austin Semi

Parameters

Alt

Parameters

Min

Max

Min

Max

Min

Max

Chip Enable Access Time

20

25

45

ns

13

Read Cycle Time

20

25

45

ns

14

Address Access Time

20

25

45

ns

Output Enable to Data Valid

10

12

20

ns

14

Output Hold After Address Change

2

2

2

ns

12, 15

Chip Enable to Output Active

2

2

2

ns

12, 15

Chip Disable to Output Active

8

10

15

ns

12, 15

Output Enable to Output Active

0

0

0

ns

12, 15

Output Disable to Output Inactive

8

10

15

ns

12

Chip Enable to Power Active

0

0

0

ns

12

Chip Disable to Power Standby

20

25

45

ns

Byte Enable to Data Valid

10

12

20

ns

12

Byte Enable to Output Active

0

0

0

ns

12

Byte Disable to Output Inactive

8

10

15

ns

Write Cycle Time

20

25

45

ns

Write Pulse Width

15

20

30

ns

Chip Enable to End of Write

15

20

30

ns

Data Setup to End of Write

8

10

15

ns

Data Hold After End of Write

0

0

0

ns

Address Setup to End of Write

15

20

30

ns

Address Setup to End of Write

0

0

0

ns

Address Hold After End of Write

0

0

0

ns

12, 15, 16

Write Enable to Output Disable

8

10

15

ns

12, 15

Output Active after End of Write

2

2

2

ns

Byte Enable to End of Write

15

20

30

ns

SRAM Read Cycle

SRAM Write Cycle

Parameters

Description

20 ns

25 ns

45 ns

Unit