AS5SP128K36DQ

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Revision 1.0 03/22/04

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2

COTS PEM

AS5SP128K36DQ

Austin Semiconductor, Inc.

SSRAM

Pin Description/Assignment Table

Logic Block Diagram

ADSP\

BWd\

BWc\

BWb\

BWa\

BWE\

GW\

ADV\

CLK

ADSC\

ADDRESS

REGISTER

Burst

Counter

and

Logic

CLR

Q0

Q1

Byte Write

Register

DQd, DQPd

Byte Write

Register

Byte Write

Register

Byte Write

Register

DQc, DQPc

DQb, DQPb

DQa, DQPa

Enable

Register

Byte Write

Driver

Byte Write

Driver

Byte Write

Driver

Byte Write

Driver

DQd, DQPd

DQc, DQPc

DQb, DQPb

DQa, DQPa

Pipeline

Enable

CE1\

CE2

CE3\

Memory

Array

Sense

Amps

Output

Registers

Output

Buffers

DQx,

DQPx

Input

Registers

Sleep

Control

OE\

ZZ

2 A0, A1

MODE

A0, A1, Ax

Signal Name

Symbol

Type

Pin

Description

Clock

CLK

Input

89

This input registers the address, data, enables, Global and Byte

writes as well as the burst control functions

Address

A0, A1

Input

37, 36

Low order, Synchronous Address Inputs and Burst counter

address inputs

Address

A

Input(s)

35, 34, 33, 32, 31, 100, Synchronous Address Inputs

99, 82, 81, 44, 45, 46,

47, 48, 49, 50

Chip Enable

CE1\, CE3\

Input

98, 92

Active Low True Chip Enables

Chip Enable

CE2

Input

97

Active High True Chip Enable

Global Write Enable

GW\

Input

88

Active Low True Global Write enable. Write to all bits

Byte Enables

BWa\, BWb\,

Input

93, 94, 95, 96

Active Low True Byte Write enables. Write to byte segments

BWc\, BWd\

Byte Write Enable

BWE\

Input

87

Active Low True Byte Write Function enable

Output Enable

OE\

Input

86

Active Low True Asynchronous Output enable

Address Strobe Controller

ADSC\

Input

85

Address Strobe from Controller. When asserted LOW, Address is

captured in the address registers and A0-A1 are loaded into the Burst

When ADSP\ and ADSC are both asserted, only ADSP is recognized

Address Strobe from Processor

ADSP\

Input

84

Synchronous Address Strobe from Processor. When asserted LOW,

Address is captured in the Address registers, A0-A1 is registered in

the burst counter. When both ADSP\ and ADSC\ or both asserted,

only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH

Address Advance

ADV

Input

83

Advance input Address. When asserted HIGH, address in burst

counter is incremented.

Power-Down

ZZ

Input

64

Asynchronous, non-time critical Power-down Input control. Places

the chip into an ultra low power mode, with data preserved.

Data Parity Input/Outputs

DQPa, DQPb

Input/

51, 80, 1, 30

Bidirectional I/O Parity lines. As inputs they reach the memory

DQPc, DQPd

Output

array via an input register, the address stored in the register on the

rising edge of clock. As and output, the line delivers the valid data

stored in the array via an output register and output driver. The data

delieverd is from the previous clock period of the READ cycle.

Data Input/Outputs

DQa, DQb, DQc

Input/

52, 53, 56, 57, 58, 59,

Bidirectional I/O Data lines. As inputs they reach the memory

DQd

Output

62, 63, 68, 69, 72, 73,

array via an input register, the address stored in the register on the

74, 75, 78, 79, 2, 3, 6,

rising edge of clock. As and output, the line delivers the valid data

7, 8, 9, 12, 13, 18, 19,

stored in the array via an output register and output driver. The data

22, 23, 24, 25, 28, 29

delieverd is from the previous clock period of the READ cycle.

Burst Mode

MODE

Input

31

Interleaved or Linear Burst mode control

Power Supply [Core]

VDD

Supply

91, 15, 41, 65

Core Power Supply

Ground [Core]

VSS

Supply

90, 17, 40, 67

Core Power Supply Ground

Power Supply I/O

VDDQ

Supply

4, 11, 20, 27, 54, 61,

Isolated Input/Output Buffer Supply

70, 77

I/O Ground

VSSQ

Supply

5, 10, 21, 26, 55, 60,

Isolated Input/Output Buffer Ground

71, 76

No Connection(s)

NC

NA

14, 16, 38, 39, 66

No connections to internal silicon

38,39,42,43