AUSTIN SEMICONDUCTOR, INC.

SSRAM

SSRAM

SSRAM

SSRAM

SSRAM

AS5SP1M36DQ

AS5SP1M36DQ

Rev. 1.2 4/09

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

4

Austin Semiconductor, Inc.

FUNCTIONAL OVERVIEW

All synchronous inputs pass through input registers

controlled by the rising edge of the clock. All data outputs

pass through output registers controlled by the rising edge

is 3.2ns (200-MHz device).

The AS5SP1M36DQ supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486

∀!

processors. The linear burst sequence is suited for

processors that utilize a linear burst sequence. The burst

order is user selectable, and is determined by sampling the

MODE input. Accesses can be initiated with either the

Processor Address Strobe (ADSP) or the Controller Address

Strobe (ADSC). Address advancement through the burst

sequence is controlled by the ADV input. A two-bit on-chip

wraparound burst counter captures the first address in a

burst sequence and automatically increments the address

for the rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable

Enable (GW) overrides all Byte Write inputs and writes data

to all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.

asynchronous Output Enable (OE) provide for easy bank

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if

(A) is stored into the address advancement logic and the

Address Register while being presented to the memory array.

The corresponding data is allowed to propagate to the input

of the Output Registers. At the rising edge of the next clock

the data is allowed to propagate through the output register

and onto the data bus within 3.2ns (200-MHz device) if OE is

active LOW. The only exception occurs when the SRAM is

emerging from a deselected state to a selected state, its

outputs are always tri-stated during the first cycle of the

access. After the first cycle of the access, the outputs are

controlled by the OE signal. Consecutive single Read cycles

are supported. Once the SRAM is deselected at clock rise by

the chip select and either ADSP or ADSC signals, its output

will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)

to A is loaded into the address register and the address

advancement logic while being delivered to the memory array.

ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise,

the data presented to the DQs inputs is written into the

corresponding address location in the memory array. If GW

is HIGH, then the Write operation is controlled by BWE and

The AS5SP1M36DQ provides Byte Write capability that is

described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.

Because AS5SP1M36DQ is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting

data to the DQs inputs.Doing so will tri-state the output drivers.

As a safety precaution, DQs are utomatically tri-stated

whenever a Write cycle is detected, regardless of the state of

OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following

conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP

and (4) the appropriate combination of the Write inputs (GW,

desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to the DQs is written into the

corresponding address location in the memory core. If a Byte

Write is conducted, only the selected bytes are written. Bytes

not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been

provided

to

simplify

the

Write

operations.

Because AS5SP1M36DQ is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting

data to the DQs inputs. Doing so will tri-state the output drivers.

As a safety precaution, DQs are automatically tri-stated

whenever a Write cycle is detected, regardless of the state of

OE.