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AS4DDR264M65PBG1 Datasheet(PDF) 7 Page - Austin Semiconductor |
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AS4DDR264M65PBG1 Datasheet(HTML) 7 Page - Austin Semiconductor |
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7 / 28 page  iiiiiPEM PEM PEM PEM PEM 4.2 G 4.2 G 4.2 G 4.2 G 4.2 Gbbbbb SDRAM-DDR2 SDRAM-DDR2 SDRAM-DDR2 SDRAM-DDR2 SDRAM-DDR2 AS4DDR264M65PBG1 AS4DDR264M65PBG1 Rev. 0.5 06/08 Austin Semiconductor, Inc. ● Austin, Texas ● 512.339.1188 ● www.austinsemiconductor.com 7 Austin Semiconductor, Inc. MODE REGISTER (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CL, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 5. Contents of the mode register can be altered by re-executing the LOAD MODE (LM) command. If the user chooses to modify only a subset of the MR variables, all variables (M0–M14) must be programmed when the command is issued. The mode register is programmed via the LM command (bits BA2–BA0 = 0, 0,0) and other bits (M13–M0) will retain the stored information until it is programmed again or the device loses power (except for bit M8, which is selfclearing). Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The LM command can only be issued (or reissued) when all banks are in the precharged state (idle state) and no bursts are in progress. The controller must wait the specified time t MRD before initiating any subsequent operations such as an ACTIVE command. Violating either of these requirements will result in unspecified operation. BURST LENGTH Burst length is defined by bits M0–M3, as shown in Figure 5. Read and write accesses to the DDR2 SDRAM are burst- oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. FIGURE 5 – MODE REGISTER (MR) DEFINITION BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved. The burst type is selected via bit M3, as shown in Figure 5. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst mode only. For 8-bit burst mode, full interleave address ordering is supported; however, sequential address ordering is nibble-based. Burst Length CAS# BT PD A9 A7 A6 A5 A4 A3 A8 A2 A1 A0 Mode Register (Mx) Address Bus 9 7 6 5 4 3 8 2 1 0 A10 A12 A11 BA0 BA1 10 11 12 n 0 0 14 Burst Length Reserved Reserved 4 8 Reserved Reserved Reserved Reserved M0 0 1 0 1 0 1 0 1 M1 0 0 1 1 0 0 1 1 M2 0 0 0 0 1 1 1 1 0 1 Burst Type Sequential Interleaved M3 CAS Latency (CL) Reserved Reserved Reserved 3 4 5 6 7 M4 0 1 0 1 0 1 0 1 M5 0 0 1 1 0 0 1 1 M6 0 0 0 0 1 1 1 1 0 1 Mode Normal Test M7 15 DLL TM 0 1 DLL Reset No Yes M8 Write Recovery Reserved 2 3 4 5 6 7 8 M9 0 1 0 1 0 1 0 1 M10 0 0 1 1 0 0 1 1 M11 0 0 0 0 1 1 1 1 WR An 2 MR M16 0 1 0 1 Mode Register Definition Mode register (MR) Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) M15 0 0 1 1 M12 0 1 PD Mode Fast exit (normal) Slow exit (low power) Latency 16 BA2 1 Notes: 1.A13 Not used on this part, and must be programmed to ‘0’ on this part. 2.BA2 must be programmed to “0” and is reserved for future use. 1 2 1 |
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