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ACS761ELF-20B Datasheet(PDF) 3 Page - Allegro MicroSystems |
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ACS761ELF-20B Datasheet(HTML) 3 Page - Allegro MicroSystems |
3 / 14 page 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC ACS761ELF-20B 3 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com Terminal List Table Number Name Function 1-6 IP+ Primary sampled current conduction path input; power input pins: connected to VCC. 7 EN Enable pin. The falling edge on the EN pin clears an overpower, overcurrent, or short circuit fault. 8 VIOUT Analog output. Output voltage on this pin is proportional to the current flowing from the IP+ pins to the IP– pins. 9 NC No connect. Connection to ground is recommended. 10 CG Terminal for CG capacitor. May be used to adjust the turn-on time and soft start control of an external MOSFET, S1. Voltage on this pin limits inrush current through MOSFET S1. Set via external capacitance, CG, connected between this pin and GND. This capacitor is charged by an internal 20 μA current source. 11 OCDLY Terminal for external capacitor, COCD, Used to adjust delay for overcurrent shutdown, set via the external capacitor, COCD, connected between this pin and GND. 12 OPDLY Terminal for external capacitor, COPD, Used to adjust delay for overpower shutdown, set via the external capacitor, COPD, connected between this pin and GND. 13 ¯F¯¯A¯U¯¯L¯¯T¯ Active low; output signal for device short circuit and overpower faults. Connect a pull-up resistor between this pin and the 3.3 V rail. 14 ¯P¯¯G¯¯O¯¯O¯¯D¯ Active low; output signal indicating load voltage has risen to the proper level. 15 FB+ Input of positive feedback on output voltage. Used to determine overpower fault threshold by difference between FB+ and GND pins. 16 PGOOD Active high; output signal indicating load voltage has risen to the proper level. 17 GND Terminal for ground connection. 18 GATE Terminal for external MOSFET, S1. Provides output voltage to drive S1. Current through S1 is controlled at start- up by external capacitance connected between the CG pin and GND. 19-24 IP– Primary sampled current conduction path output; power output pins. Pin-out Diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 IP– IP– IP– IP– IP– IP– GATE GND PGOOD FB+ PGOOD FAULT IP+ IP+ IP+ IP+ IP+ IP+ EN VIOUT NC CG OCDLY OPDLY |
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