M12L128324A-6TIG datasheet(4/49 Pages) ESMT

Part #	M12L128324A-6TIG

Description	1M x 32 Bit x 4 Banks Synchronous DRAM

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Manufacturer	ESMT [Elite Semiconductor Memory Technology Inc.]

Direct Link	http://www.esmt.com.tw/index.asp

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4 / 49 page

ESMT

M12L128324A

Operation temperature condition -40

°C~85°C

Elite Semiconductor Memory Technology Inc.

Publication Date: Feb. 2006

Revision: 1.1

4/49

DQM0~3

DQ

Mode

Register

Column

Address

Buffer

&

Refresh

Counter

Row

Address

Buffer

&

Refresh

Counter

Bank D

Bank A

Bank B

Bank C

Sense Amplifier

Column Decoder

Data Control Circuit

Address

Clock

Generator

CLK

CKE

CS

RAS

CAS

WE

BLOCK DIAGRAM

PIN DESCRIPTION

NAME

INPUT FUNCTION

CLK

System Clock

Active on the positive going edge to sample all inputs

CS

Chip Select

Disables or enables device operation by masking or enabling all

inputs except CLK , CKE and DQM0-3.

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior new command.

Disable input buffers for power down in standby.

A0 ~ A11

Address

Row / column address are multiplexed on the same pins.

Row address : RA0~RA11, column address : CA0~CA7

BA0 , BA1

Bank Select Address

Selects bank to be activated during row address latch time.

Selects bank for read / write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with

RAS low.

Enables row access & precharge.

CAS

Column Address Strobe

Latches column address on the positive going edge of the CLK with

CAS low.

Enables column access.

WE

Write Enable

Enables write operation and row precharge.

Latches data in starting from CAS , WE active.

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