ESMT

M12L128168A

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 2.3

8/45

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address

BA0~BA1

A11~A10/AP

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Function

RFU

RFU

W.B.L.

TM

CAS Latency

BT

Burst Length

Test Mode

CAS Latency

Burst Type

Burst Length

A8

A7

Type

A6

A5

A4

Latency

A3

Type

A2

A1

A0

BT = 0

BT = 1

0

0

Mode Register Set

0

0

0

Reserved

0

Sequential

0

0

0

1

1

0

1

Reserved

0

0

1

Reserved

1

Interleave

0

0

1

2

2

1

0

Reserved

0

1

0

2

0

1

0

4

4

1

1

Reserved

0

1

1

3

0

1

1

8

8

1

0

0

Reserved

1

0

0

Reserved Reserved

1

0

1

Reserved

1

0

1

Reserved Reserved

1

1

0

Reserved

1

1

0

Reserved Reserved

1

1

1

Reserved

1

1

1

Full Page Reserved

Full Page Length : 512

POWER UP SEQUENCE

1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.

2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note :

1. RFU(Reserved for future use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “ Burst Read single write” function will be enabled.