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| M12L32162A_0712 |
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19 page 
ESMT M12L32162A Operation Temperature Condition -40°C~105°C Elite Semiconductor Memory Technology Inc. Publication Date : Dec. 2007 Revision : 1.2 19/28 Read & Write Cycle with auto Precharge @ Burst Length =4 *Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start (In the case of Burst Length=1 & 2 and BRSW mode) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CL OC K CK E CA S AD DR WE DQ DQ M A1 0 / A P BA CL = 2 CL = 3 Row Active ( A - Bank ) Row Active ( B - Bank ) Read with Auto Precharge ( A - Bank ) Au t o P r ec h a r g e S t a r t P o i n t ( B - B ank ) : D o n ' t C a r e Qa1 Q a2 Qa3 Db 1 Db 2 D b 3 Db 0 Qa0 Ra Cb Ra C a Rb Rb Qa1 Qa2 Qa3 Db 1 D b 2 Db 3 Db 0 Qa0 W r i t e wi t h A u to P r e c h a rg e (B -B a n k ) HIGH Auto Precharge Start Point ( A - Bank) CS RA S |
