ESMT

(Preliminary)

F25S04PA

Elite Semiconductor Memory Technology Inc.

9/34

INSTRUCTIONS

Instructions are used to Read, Write (Erase and Program), and

configure the F25S04PA. The instruction bus cycles are 8 bits

each for commands (Op Code), data, and addresses. Prior to

executing any Page Program, Write Status Register, Sector

Erase, Block Erase, or Chip Erase instructions, the Write Enable

(WREN) instruction must be executed first. The complete list of

the instructions is provided in Table 5. All instructions are

synchronized off a high to low transition of CE . Inputs will be

accepted on the rising edge of SCK starting with the most

significant bit. CE must be driven low before an instruction is

entered and must be driven high after the last bit of the instruction

has been shifted in (except for Read, Read ID, Read Status

Register, Read Electronic Signature instructions). Any low to high

transition on CE , before receiving the last bit of an instruction

bus cycle, will terminate the instruction in progress and return the

device to the standby mode.

Instruction commands (Op Code), addresses, and data are all

input from the most significant bit (MSB) first.

Table 5: Device Operation Instructions

Bus Cycle

1~3

1

2

3

4

5

6

N

Operation

Max.

Freq

Read

X

X

X

cont.

Fast Read

0BH

X

X

X

X

cont.

Fast Read Dual

Output

11,12

3BH

X

cont.

Sector Erase

20H

-

-

-

-

-

-

Block Erase

D8H

-

-

-

-

-

-

Chip Erase

60H /

C7H

Hi-Z

-

-

-

-

-

-

-

-

-

-

-

-

Page Program (PP)

02H

Hi-Z

Hi-Z

Up to

256

bytes

Hi-Z

Read Status Register

(RDSR)

6

05H

Hi-Z

X

-

-

-

-

-

-

-

-

-

-

Write Status Register

(WRSR)

01H

Hi-Z

Hi-Z

-

-

-.

-

-

-

-

-

-

-

Write Enable (WREN)

9

06H

Hi-Z

-

-

-

-

-

-

-

-

-

-

-

-

Write Disable (WRDI)

04H

Hi-Z

-

-

-

-

-

-

-

-

-

-

-

-

Deep Power Down (DP)

B9h

Hi-Z

-

-

-

-

-

-

-

-

-

-

-

-

Release from Deep

Power Down (RDP)

ABH

Hi-Z

-

-

-

-

-

-

-

-

-

-

-

-

Read Electronic

Signature (RES)

7

ABH

Hi-Z

X

X

X

X

X

X

X

12H

-

-

-

-

Jedec Read ID

(JEDEC-ID)

8

9FH

Hi-Z

X

8CH

X

20H

X

13H

-

-

-

-

-

-

00H

Hi-Z

X

8CH

X

12H

-

-

Read ID (RDID)

10

~

90H

Hi-Z

00H

Hi-Z

00H

Hi-Z

01H

Hi-Z

X

12H

X

8CH

-

-

Note:

1.

2.

3.

One bus cycle is eight clock periods.

4.

5.

To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be

programmed.

6.

The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .

7.

The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .

8.

The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 13H as

memory capacity.

9.

The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each

other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both