ESMT

F25S004A

Elite Semiconductor Memory Technology Inc.

Publication Date: Jan. 2009

10/33

capacity.

11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.

The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions

effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.

Read (33 MHz)

The Read instruction supports up to 33 MHz, it outputs the data

starting from the specified address location. The data output

stream is continuous through all addresses until terminated by a

low to high transition on CE . The internal address pointer will

automatically increment until the highest memory address is

reached. Once the highest memory address is reached, the

address pointer will automatically increment to the beginning

(wrap-around) of the address space, i.e. for 4Mbit density, once

the data from address location 7FFFFH had been read, the next

output will be from address location 00000H.

The Read instruction is initiated by executing an 8-bit command,

low for the duration of the Read cycle. See Figure 2 for the Read

sequence.

Figure 2 : READ SEQUENCE

CE

SCK

SI

1 2 3 4 5 6 7 8

15 16

23 24

31 32

39 40

47 48

55 56

63 64

70

N+4

N+3

N+2

N+1

N

MSB

MSB

MSB

HIGH IMPENANCE

SO

03

MODE3

MODE1

ADD.

ADD.

ADD.