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F25L004A-50PIG Datasheet(PDF) 19 Page - Elite Semiconductor Memory Technology Inc. |
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F25L004A-50PIG Datasheet(HTML) 19 Page - Elite Semiconductor Memory Technology Inc. |
19 / 33 page ESMT F25L004A Operation Temperature Condition -40 C ° ~85 C ° Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.3 19/33 Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. Write-Status-Register (WRSR) The Write-Status-Register instruction writes new values to the BP2, BP1, BP0, and BPL bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 15 for EWSR or WREN and WRSR instruction sequences. Executing the Write-Status-Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lockdown the status register, but cannot be reset from “1” to “0”. When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 ;BP1 and BP2 bits at the same time. See Table 3 for a summary description of WP and BPL functions. Figure 15 : ENABLE-WRITE-STATUS-REGISTER (EWSR) or WRITE-ENABLE(WREN) and WRITE-STATUS-REGISTER (WRSR) CE SCK SI 01 234 56 7 MSB MSB HIGH IMPENANCE SO 50 or 06 MODE3 MODE0 0 1 2 345 67 8 9 1011 12 13 1415 STATUS REGISTER IN 01 7 6 5 4 3 2 1 0 |
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