Multiprotocol, Pin-Selectable

Data Interface Chipset

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9

MAX13175E. Specifications over temperature are guaranteed by design.

Note 3: Guaranteed by design, not production tested.

Note 4: Output-to-output skews are evaluated as difference of propagation delays between different channels in the same condition

and for the same polarity (LH or HL).

Note 5: M[x] is the input bus DTE/DCE, M2, M1, M0.

MAX13175E ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

cable mode, Figure 12

100

104

110

Differential-Mode Impedance

V.11 Mode

115

Ω

Differential Path Enable Time

50

µs

Differential Path Disable Time

300

µs

Common-Mode Path Enable Time

12

µs

Common-Mode Path Disable

Time

2µs

High-Impedance Leakage

Current

-50

+50

µA

LOGIC INPUTS (M0, M1, M2,

LATCH, DCE/DTE)

Input High Voltage

V

Input Low Voltage

V

Logic Input Current

-1

+1

µA

ESD PROTECTION

Human Body Model

±15

Air Gap Discharge IEC 61000-4-2

±10

R_A, R_B to GND

Contact Discharge IEC 61000-4-2

±6

kV

All Other Pins

Human Body Model

±2

kV