21-Bit Deserializers with Programmable

Spread Spectrum and DC Balance

6

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Test Circuits/Timing Diagrams

RxIN_ + OR

RxCLKIN+

RxIN_ - OR

RxCLKIN-

RxIN_ + OR

RxCLKIN+

RxIN_ - OR

RxCLKIN-

FAIL-SAFE

COMPARATOR

DC-BALANCED MODE

NON-DC-BALANCED MODE

1.2V

Figure 1. LVDS Input Circuits

RCOP

RxCLKOUT

ODD RxOUT

EVEN RxOUT

Figure 2. Worst-Case Test Pattern

90%

90%

10%

10%

CHLT

CLHT

RxOUT_ OR

RxCLKOUT

RxOUT_ OR

RxCLKOUT

8pF

Figure 3. Output Load and Transition Times

IDEAL

MIN

MAX

INTERNAL STROBE

IDEAL

RSKM

RSKM

IDEAL SERIAL BIT TIME

1.3V

1.1V

Figure 4. LVDS Receiver Input Skew Margin

RxOUT_

RxCLK OUT

RCOP

RCOH

RCOL

2.0V

0.8V

2.0V

0.8V

2.0V

2.0V

2.0V

0.8V

0.8V

RHRC

RSRC

Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times