27-Bit, 2.5MHz-to-42MHz

DC-Balanced LVDS Serializer

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9

BIT 0

BIT 19

N

N + 3

EXPANDED TIME SCALE

N + 4

N

N + 1

N + 2

N - 1

RGB_IN

CNTL_IN

PCLK_IN

OUT_

Figure 5. Serializer Delay

HIGH IMPEDANCE

PWRDWN

(OUT+) - (OUT-)

PCLK_IN

Figure 6. PLL Lock Time

HIGH IMPEDANCE

PWRDWN

(OUT+) - (OUT-)

PCLK_IN

Figure 7. Power-Down Delay