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MAX149ACAP Datasheet(PDF) 8 Page - Maxim Integrated Products |
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MAX149ACAP Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 23 page +2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs 8 ______________________________________________________________________________________ Detailed Description The MAX148/MAX149 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 10-bit digital output. A flexible serial interface provides easy interface to microproces- sors (FPs). Figure 3 is a block diagram of the MAX148/ MAX149. Pseudo-Differential Input The sampling architecture of the ADC’s analog com- parator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0–CH7, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels with Tables 2 and 3. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within Q0.5 LSB (Q0.1 LSB for best results) with respect to AGND during a conversion. To accomplish this, con- nect a 0.1FF capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisi- tion interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the comparator’s input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0 within the limits of 10-bit resolution. This action is equivalent to transferring a 16pF x [(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. Track/Hold The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the “+” input. If the converter is set up for dif- ferential inputs, IN- connects to the “-” input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, and more time must be Figure 3. Block Diagram Figure 4. Equivalent Input Circuit CS SHDN SCLK DIN CH0 1 18 15 16 20 14 13 19 INPUT SHIFT REGISTER OUTPUT SHIFT REGISTER ANALOG INPUT MUX CLOCK IN 10+2-BIT SAR ADC +1.21V REFERENCE (MAX149) REF OUT T/H CONTROL LOGIC INT CLOCK 17 10 2 3 4 5 6 7 8 9 12 11 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM DOUT SSTRB VDD DGND AGND +2.500V 20k Ω *A ≈ 2.00 (MAX148) A ≈ 2.06* REFADJ VREF MAX148 MAX149 COM CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7. AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. COMPARATOR CAPACITIVE DAC CSWITCH TRACK T/H SWITCH RIN 9k Ω CHOLD HOLD VREF ZERO 16pF INPUT MUX - + |
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