_______________________________________________________________________________________

7

Step Control Register (SCR)

SCR determines the stepping functionality for the RW

and Y potentiometers (see the

Stepping section). The

five LSBs, bits 4:0, control the STEPCOUNT, which is

the number of steps up and down the wiper moves

when stepping is enabled. Bits 5 and 6 control the

PERIOD, which is the number of pulses of the SYNC pin

required to perform one step.

Setting STEPCOUNT to all zeros disables stepping for the

DS3503. A STEPCOUNT of 1 is an invalid setting. The

DS3503 should not be programmed with a STEPCOUNT

value of 00001.

Control Register (CR)

data is written to IVR/WR at 00h. When CR is set to a

writes to memory address 00h write only to WR.

00h return the contents of WR.

to both the IVR and WR locations. The data that is

stored in EEPROM and SRAM remains unchanged if

the value of CR is changed. Table 3 defines CR.

Stepping

The DS3503 can step the RW output up to WR+STEP-

COUNT and down to WR-STEPCOUNT when stepping

is enabled. Stepping is enabled when a nonzero STEP-

COUNT value is programmed into SCR and pulses are

applied to the SYNC input pin. Stepping is disabled

when STEPCOUNT = 0 or no pulses are applied on the

SYNC input pin. STEPCOUNT = 1 is an invalid setting.

The falling edge of the SYNC pulse updates the out-

puts. The Y potentiometer output is created by adding

to position 40h (code 64 decimal) the same counter

value as is added to WR to form the input to the RW

potentiometer.

The WR value is internally limited (clamped) to a minimum

of STEPCOUNT and maximum of 127 - STEPCOUNT.

When stepping is enabled, the RW wiper position is

controlled by WR plus a counter value (COUNT in the

Functional Diagram). COUNT increments or decre-

ments when the number of SYNC pulses received since

the last COUNT change is equal to PERIOD. SCR bits

6:5 set PERIOD equal to 32, 64, 128, or 256 SYNC puls-

es (see Table 2).

or SCR, stepping is initially disabled until 512 plus

BIT

NAME

FUNCTION

4:0

STEPCOUNT

Bit 4 is the MSB; bit 0 is the LSB. These 5 bits define the number of steps in an up or down cycle.

Maximum is 31, minimum is 2. A STEPCOUNT of zero corresponds to a disabled counter.

0, 0: PERIOD = 32 SYNC pulses

0, 1: PERIOD = 64 SYNC pulses

1, 0: PERIOD = 128 SYNC pulses

6:5

PERIOD

1, 1: PERIOD = 256 SYNC pulses

7

—

Reserved

Table 2. Step Control Register Description (01h)

BIT

NAME

FUNCTION

6:0

—

Reserved

7

IVR/WR

ADDRESS

MODE

0: Read WR; write IVR and WR at address 00h.

1: Read WR; write WR at address 00h.

Table 3. Control Register Description (02h)