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DS3100 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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DS3100 Datasheet(HTML) 10 Page - Maxim Integrated Products |
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10 / 227 page  DS3100 19-4546; Rev 9; 5/09 10 of 227 4. DETAILED DESCRIPTION Figure 2-1 illustrates the blocks described in this section and how they relate to one another. Section 5 provides a detailed feature list. The DS3100 is a complete timing card IC for systems with SONET/SDH ports. At the core of this device are two digital phase-locked loops (DPLLs) labeled T0 and T4 1. DPLL technology makes uses of digital-signal processing (DSP) and digital-frequency synthesis (DFS) techniques to implement PLLs that are precise, flexible, and have consistent performance over voltage, temperature, and manufacturing process variations. The DS3100’s DPLLs are digitally configurable for input and output frequencies, loop bandwidth, damping factor, pull-in/hold-in range, and a variety of other factors. Both DPLLs can directly lock to many common telecom frequencies and also can lock at 8kHz to any multiple of 8kHz up to 155.52MHz. The DPLLs can also tolerate and filter significant amounts of jitter and wander. The T0 DPLL is responsible for generating the system clocks used to time the outgoing traffic interfaces of the system (SONET/SDH, synchronous Ethernet, etc.). To perform this role in a variety of systems with diverse performance requirements, the T0 DPLL has a sophisticated feature set and is highly configurable. T0 can automatically transition among free-run, locked and holdover states all without software intervention. In free-run, T0 generates a stable, low-noise clock with the same frequency accuracy as the external oscillator connected to the REFCLK pin. With software calibration the DS3100 can even improve the accuracy to within ±0.02 ppm. When an input reference has been validated, T0 transitions to the locked state in which its output clock accuracy is equal to the accuracy of the input reference. While in the locked state, T0 acquires a high-accuracy (3.85 x10 -11) long-term average frequency value to use as the holdover frequency. When its selected reference fails, T0 can very quickly detect the failure and enter the holdover state to avoid affecting its output clock. From holdover it can automatically switch to the next highest priority input reference, again without affecting its output clock (hitless switching). Switching among input references can be either revertive or nonrevertive. When all input references are lost, T0 stays in holdover in which it generates a stable low-noise clock with initial frequency accuracy equal to its stored holdover value and drift performance determined by the quality of the external oscillator. With a suitable local oscillator the T0 DPLL provides holdover performance suitable for all applications up to and including Stratum 2. T0 can also perform phase build-outs and fine-granularity output clock phase adjustments. The T4 DPLL has a much less demanding role to play and therefore is much simpler than T0. Often T4 is used as a frequency converter to create a derived DS1- or E1-rate clock (frequency locked to an incoming SONET/SDH port) to be sent to a nearby BITS Timing Signal Generator (TSG, Telcordia terminology) or Synchronization Supply Unit (SSU, ITU-T terminology). In other cases T4 is phase-locked to T0 and used as a frequency converter to produce additional output clock rates for use within the system, such as NxDS1, NxE1, NxDS2, DS3, E3, or 125MHz for synchronous Ethernet. T4 can also be configured as a measuring tool to measure the frequency of an input reference or the phase difference between two input references. At the front end of both the T0 and T4 DPLLs is the Input Clock Selector, Divider, and Monitor (ICSDM) block. This block continuously monitors as many as 14 different input clocks of various frequencies for activity and frequency accuracy. In addition, ICSDM maintains separate input clock priority tables for the T0 and T4 DPLLs and can automatically select and provide the highest priority valid clock to each DPLL without any software intervention. The ICSDM block can also divide the selected clock down to 8kHz if required by the DPLL. In addition to digital clock signals from system line cards, the DS3100 can also directly receive up to two 64kHz composite clock signals on its IC1A and IC2A pins and up to two DS1, E1, 2048kHz, or 6312kHz synchronization signals using its BITS receivers. These signals typically come from a nearby BITS Timing Signal Generator or SSU to provide external timing to the system. The BITS receivers are full-featured LIU receivers and framers capable of recovering clock and data from both short-haul and long-haul signals, finding DS1/E1 frame, extracting incoming SSM messages, and reporting both SSMs and performance defects (LOS, OOF, AIS, RAI) to system software. The recovered clock from each BITS receiver can be connected to any of the 14 input clocks of the ICSDM block for monitoring, optional dividing, and selection as the reference for either of the DPLLs. The BITS receivers are tightly coupled to the ICSDM block, and the DS3100 can be configured to automatically disqualify input clocks from BITS receivers (or take other actions) when defects are detected. The analog front-ends of the BITS receivers are state- 1 These names are adapted from output ports of the SETS function specified in ITU and ETSI standards such as ETSI EN 300 462-2-1. |
Similar Part No. - DS3100_09 |
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Similar Description - DS3100_09 |
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