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V•I Chip Voltage Transformation Module

V048F040T050

Rev. 2.7

Page 10 of 11

V•I Chip Voltage Transformation Module

-In

PC

VC

TM

+In

-Out

+Out

VTM

+Out

-Out

K

Ro

+Out

–Out

+In

–In

VC

PC

TM

IL

VH

PR

NC

SG

SC

PRM-AL

OS

NC

CD

L

O

A

D

Factorized

(Io•Ro)

K

K

Vin

FPA Adaptive Loop

Figure 19 — An external error amplifier or Point-of-Load IC (POLIC) senses the load voltage and controls the PRM output – the Factorized Bus – as a function of

output current, compensating for the output resistance of the VTM and for distribution resistance.

+Out

–Out

+In

–In

VC

PC

TM

IL

VH

PR

NC

SG

SC

PRM-AL

OS

NC

CD

-In

PC

VC

TM

+In

-Out

+Out

VTM

+Out

-Out

K

Ro

Remote

Loop

Control

L

O

A

D

Factorized

Power Bus

+S

–S

Vin

FPA Non-isolated Remote Loop

In figures below;

K = VTM transformation ratio

+

–

+

–

V

K

+

–

+

–

81 mA

V•I Chip VTM Level 2 Transient Behavioral Model for 48 V to 4 V, 50 A

Figure 17 — This model characterizes the AC operation of the V•I Chip VTM including response to output load or input voltage transients or steady state

modulations. The model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load

with or without external filtering elements.

©

1/12 • Iout

1/12 • Vin

2.8 mΩ

1.3 mΩ

0.23 nH

0.96 mΩ

0.7 mΩ

255 µF

1.9 µF