NCP1631 datasheet(11/23 Pages) ONSEMI

Part #	NCP1631

Description	Interleaved, 2-Phase Power Factor Controller

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Manufacturer	ONSEMI [ON Semiconductor]

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NCP1631

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0

2

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1012

1416

1820

time (ms)

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3,50

Vin

ton

Figure 8. Input Voltage and On−time vs. Time (example with FSW = 100 kHz, Pin = 150 W, VAC = 230 V, L = 200 mH)

Regulation Block and Low Output Voltage Detection

A trans−conductance error amplifier with access to the

inverting input and output is provided. It features a typical

trans−conductance gain of 200

mS and a typical capability

of

±20 mA. The output voltage of the PFC stage is typically

scaled down by a resistors divider and monitored by the

inverting input (feed−back pin – pin2). The bias current is

minimized (less than 500 nA) to allow the use of a high

impedance feed−back network. The output of the error

amplifier is pinned out for external loop compensation

(pin5). Typically a type−2 compensator is applied between

pin5 and ground, to set the regulation bandwidth below

20 Hz, as need in PFC applications (refer to application

note AND8407).

The swing of the error amplifier output is limited within

an accurate range:

• It is forced above a voltage drop (VF) by the “low

clamp” circuitry. When this circuitry is activated, the

power demand is minimum and the NCP1631 enters

skip mode (the controller stops pulsating) until the

clamp is no more active.

• It is clamped not to exceed 3.0 V + the same VF

voltage drop.

Hence, Vpin5 features a 3 V voltage swing. Vpin5 is then

offset down by (VF) and further divided before it connects

to the “Vton processing block” and the PWM section.

Finally, the output of the regulation is a signal (“VREGUL”

of the block diagram) that varies between 0 and 1.66 V.

Figure 9. Regulation Block

FB

Vcontrol

OFF

Error Amplifier

Vref

0.955*Vref

Vout low

detect

±20 mA

3V

5R

pfcOK

230 mA

VDD

OVLflag1

4R

SKIP

Figure 10. Correspondence Between

VCONTROL and VREGUL

VREGUL

(0.6 V clamp

voltage is activated)

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