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SPT7721SIT Datasheet(PDF) 8 Page - Cadeka Microcircuits LLC. |
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SPT7721SIT Datasheet(HTML) 8 Page - Cadeka Microcircuits LLC. |
8 / 11 page 8 11/8/01 SPT7721 TYPICAL INTERFACE CIRCUIT Very few external components are required to achieve the stated device performance. Figure 3 shows the typical interface requirements when using the SPT7721 in normal circuit operation. The following sections provide descrip- tions of the major functions and outline performance criteria to consider for achieving the optimal device performance. ANALOG INPUT The input of the SPT7721 can be configured in various ways depending on whether a single-ended or differential input is desired. The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary wind- ing. The center tap is connected to the VCM pin as shown in figure 3. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is im- portant for input signal purity. A small capacitor across the input attenuates kickback noise from the internal track- and-hold. Figure 4 illustrates a solution (based on operational ampli- fiers) that can be used if a DC-coupled single-ended input is desired. It is very important to select op amps with a high open-loop gain, a bandwidth high enough so as not to im- pair the performance of the ADC, low THD, and high SNR. INPUT PROTECTION All I/O pads are protected with an on-chip protection circuit. This circuit provides ESD robustness and prevents latchup under severe discharge conditions without degrading analog transmission times. POWER SUPPLIES AND GROUNDING The SPT7721 is operated from a single power supply in the range of 4.75 to 5.25 volts. Normal operation is sug- gested to be 5.0 volts. All power supply pins should be by- passed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible. VCM R3 (R3)/2 + Input Voltage (±0.5 V) R3 R R2 R2 + + R RR 51 W 51 W R ADC VIN+ VIN 15 pF 51 W Figure 4 – DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown) +A5 10 + +D3/5 10 T1 VIN+ VIN VCMOUT AIN Mini-Circuit T1-6T 50 Interfacing Logics +D3/5 DA0DA7 DB0DB7 Mode Select Reset Diff In Clock Diff In FB .01(2x) .01(3x) .01(3x) SPT7721 DCLKOUT DCLKOUT .01 Notes: 1) FB = Ferrite bead. It must placed as close to the ADC as possible. 2) All inputs are internally biased: a) DMode1 to GND through 100K b) DMode2 to VCC through 50K c) CLK, PD and Rest pins to GND through 100K d) /CLK and /Reset pins to 1.5 V through 5K e) VIN+ and VIN to +2.5 V through 50K 3) All 0.01microfarad capacitors are surface mount caps. They must be placed as close to the respective pin as possible }Default=interleavedual channel output Figure 3 – Typical Interface Circuit |
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