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SPT574 Datasheet(PDF) 6 Page - Cadeka Microcircuits LLC. |
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SPT574 Datasheet(HTML) 6 Page - Cadeka Microcircuits LLC. |
6 / 12 page SPT574 CIRCUIT OPERATION The SPT574 is a complete 12-bit analog-to-digital converter that consists of a single chip version of the industry standard 574. This single chip contains a precision 12-bit capacitor digital-to-analog converter (CDAC) with voltage reference, comparator, successive approximation register (SAR), sample- and-hold, clock, output buffers and control circuitry to make it possible to use the SPT574 with few external components. When the control section of the SPT574 initiates a conversion command, the clock is enabled and the successive-approxi- mation register is reset to all zeros. Once the conversion cycle begins, it cannot be stopped or restarted and data is not available from the output buffers. The SAR, timed by the clock, sequences through the conver- sion cycle and returns an end-of-convert flag to the control section of the ADC. The clock is then disabled by the control section, the output status goes low, and the control section is enabled to allow the data to be read by external command. The internal SPT574 12-bit CDAC is sequenced by the SAR starting from the MSB to the LSB at the beginning of the conversion cycle to provide an output voltage from the CDAC that is equal to the input signal voltage (which is divided by the input voltage divider network). The comparator determines whether the addition of each successively-weighted bit volt- age causes the CDAC output voltage summation to be greater or less than the input voltage; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within ±1/2 LSB. The internal reference provides the voltage reference to the CDAC with excellent stability over temperature and time. The reference is trimmed to 2.5 volts and can supply at least 0.5 mA to an external load. Any external load on the SPT574 reference must remain constant during conversion. The sample-and-hold feature is a bonus of the CDAC archi- tecture. Therefore the majority of the S/H specifications are included within the A/D specifications. Although the sample-and-hold circuit is not implemented in the classical sense, the sampling nature of the capacitive DAC makes the SPT574 appear to have a built-in sample- and-hold. This sample-and-hold action substantially in- creases the signal bandwidth of the SPT574 over that of similar competing devices. Note that even though the user may use an external sample- and-hold for very high frequency inputs, the internal sample- and-hold still provides a very useful isolation function. Once the internal sample is taken by the CDAC capacitance, the input of the SPT574 is disconnected from the user’s sample- and-hold. This prevents transients occurring during conver- sion from affecting the attached sample-and-hold buffer. All other 574 circuits will cause a transient load current on the sample-and-hold which will upset the buffer output and may add error to the conversion itself. Furthermore, the isolation of the input after the acquisition time in the SPT574 allows the user an opportunity to release the hold on an external sample-and-hold and start it tracking the next sample. This increases system throughput with the user’s existing components. TYPICAL INTERFACE CIRCUIT The SPT574 is a complete A/D converter that is fully opera- tional when powered up and issued a Start Convert Signal. Only a few external components are necessary as shown in figures 5 and 6. The two typical interface circuits are for operating the SPT574 in either an unipolar or bipolar input mode. Information on these connections and on conditions concerning board layout to achieve the best operation are discussed below. For each application of this device, strict attention must be given to power supply decoupling, board layout (to reduce pickup between analog and digital sections), and grounding. Digital timing, calibration and the analog signal source must be considered for correct operation. POWER SUPPLIES The supply voltage for the SPT574 must be kept as quiet as possible from noise pickup and also regulated from transients or drops. Because the part has 12-bit accuracy, voltage spikes on the supply lines can cause several LSB deviations on the output. Switching power supply noise can be a problem. Careful filtering and shielding should be employed to prevent the noise from being picked up by the converter. VDD should be bypassed with a 10 µF tantalum capacitor located close to the converter to filter noise and counter the problems caused by the variations in supply current. VEE is only used as a logic input and is immune to typical supply variation. GROUNDING CONSIDERATIONS Resistance of any path between the analog and digital grounds should be as low as possible to accommodate the ground currents present with this device. To achieve specified accuracy, a double-sided printed circuit board with a copper ground plane on the component side is recommended. Keep analog signal traces away from digital lines. It is best to lay the PC board out such that there is an analog section and a digital section with a single point ground connection between the two through an RF bead located as close to the device as possible. If possible, run analog signals between ground traces and cross digital lines at right angles only. 6 8/1/00 |
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