TE

CH

tm

Preliminary T35L3232B

Taiwan Memory Technology, Inc. reserves the right

P. 14

Publication Date: FEB. 2000

to change products or specifications without notice.

Revision:0.A

WRITE TIMING

BURST WRITE

C LK

ADS C

High-Z

AD S P

AD D RE S S

B W E ,

B W 1 - B W 4

t KC

t KH t KL

t ADSS t ADSH

DO N' T CARE

UNDEFINED

t AS t AH

t WS t WH

t CES t CEH

t AAS t AAH

tOEHZ

t DS t DH

Single WRITE

(NOTE3)

D(A1)

D(A2)

D(A2+1)

D(A2+2)

D(A2+3)

D(A3+1)

D(A3)

A3

A2

A1

(NOTE1)

CE

( N O T E 2 )

ADV

O E

D

ADSC extends burst.

t ADSS t ADSH

t ADSS t ADSH

G W

t WS t WH

D(A2+1)

D(A3+2)

BURST READ

Extended BURST WRITE

Q

ADV suspnds burst.

(NOTE4)

(NOTE5)

BYT E WRIT E signals are

ignored for first cycle when

ADSP initialtes burst.

Note: 1. Q(A2) refers to output from address A2.

Q (A2 + 1) refers to output from the next internal burst

address following A2.

2. CE2 and CE2 have timing identical to CE .

On this diagram, when CE is LOW , CE2 is

LOW and CE2 is HIGH.

When CE is HIGH , CE2 is HIGH and CE2 is LOW.

3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time.

This prevents input/output data contention for the time period to the byte write enable inputs being

sampled.

5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4

LOW.