UCC29421, UCC29422, UCC39421, UCC39422

MULTIMODE HIGHFREQUENCY PWM CONTROLLER

SLUS246C − OCTOBER 1999 − REVISED FEBRUARY 2005

1

POST OFFICE BOX 655303

Voltage of 1.8 V

Flyback (Buck-Boost) Topologies

High-Current Applications

Operation

with Programmable Variable

Frequency Mode

Mode

Rectification

(UCC39422 Only)

(UCC39422 Only)

description

The UCC39421 family of synchronous

PWM controllers is optimized to operate

from dual alkaline/NiCd cells or a single

Lithium-Ion (Li-Ion) cell, and convert to

adjustable output voltages from 2.5 V to

8 V. For applications where the input

voltage does not exceed the output, a

standard boost configuration is used.

For other applications where the input voltage can swing above and below the output, a 1:1 coupled inductor

(Flyback or SEPIC) is used in place of the single inductor. Fixed frequency operation can be programmed, or

synchronized to an external clock source. In applications where (at light loads) variable frequency mode is

acceptable, the IC can be programmed to automatically enter PFM (pulse frequency modulation) mode for an

additional efficiency benefit.

Synchronous rectification provides excellent efficiency at high power levels, where N- or P- type MOSFETs can

be used. At lower power levels (between 10% and 20% of full load) where fixed frequency operation is required,

low power mode is entered. This mode optimizes efficiency by cutting back on the gate drive of the charging

FET. At very low power levels, the IC enters a variable frequency mode (PFM). PFM can be disabled by the user.

Copyright

 2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

simplified schematic block diagram and

application circuit

UDG−98122

20

4

2

16

18

1

17

5

15

11

19

6

8

9

7

13

14

10

12

+

1.24 V

LOWBAT

+

200 mS

RESET/

POR

1.18 V

VDET

RSADJ

GND

UCC39422

ONLY

RESET

+

1.22V

PWM CIRCUITRY

CURRENT LIMIT

LOW POWER

MODE

SLOPE

COMPENSATION

PFM MODE

CONTROL

+

PFM

COMP

FB

ERROR

AMP

PGND

ISENSE

50 mV TYP

+

X10

ANTI−

CROSS

COND.

CHRG

VPUMP

RSEL

RECT

CHARGE

PUMP

3

CP

VOUT

RSEN

VIN

VPUMP

+

+

2 CELL

ALKALINE/

NiCd OR

1 LI−ION

VOUT

RT

SYNC/SD

PWM

OSC

1.24 V

VREF

VGD

1.24 V

1.8 V(MIN)