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CYDM064B16, CYDM128B16, CYDM256B16
Document #: 001-00217 Rev. *F
Page 2 of 24
Logic Block Diagram [1, 2]
IO
Control
Address Decode
Mailboxes
INTL
INTR
Address Decode
16K X 16
Dual Ported Array
IO
Control
Interrupt
Arbitration
Semaphore
A [13:0]R
CE R
BUSY R
IO[15:0]R
LBR
IO[15:0]L
LBL
OE L
BUSY L
A[13:0]L
R/W L
CE L
M/S
UBL
UBR
SEML
SEMR
Input Read
Register and
Output Drive
Register
CE R
OE R
OE R
R/W R
R/W R
ODR0 - ODR4
CEL
OEL
R/WL
IRR0 ,IRR1
SFEN
Notes
1. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
2. BUSY is an output in master mode and an input in slave mode.
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