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CY2305C
CY2309C
Document Number: 38-07672 Rev. *H
Page 2 of 12
Pinouts
CY2305C
Logic Block Diagram for CY2309C
PLL
MUX
Select Input
REF
S2
S1
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Decoding
CLKOUT
Figure 1. Pin Diagram - 8 Pin SOIC
Table 1. Pin Description - 8 Pin SOIC
Pin
Signal
Description
1REF[1]
Input reference frequency
2CLK2[2]
Buffered clock output
3CLK1[2]
Buffered clock output
4
GND
Ground
5CLK3[2]
Buffered clock output
6VDD
3.3V supply
7CLK4[2]
Buffered clock output
8CLKOUT[2]
Buffered clock output, internal feedback on this pin
1
2
3
4
5
8
7
6
REF
CLK2
CLK1
GND
VDD
CLKOUT
CLK4
CLK3
Top View
CY2305C
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
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