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CY29351AXI Datasheet(PDF) 5 Page - Cypress Semiconductor

Part # CY29351AXI
Description  2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY29351AXI Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY29351
Document Number: 38-07475 Rev. *C
Page 5 of 10
AC Electrical Specifications
(VDD = 2.5V ± 5%, TA = –40°C to +85°C)[7]
Parameter
Description
Condition
Min
Typ
Max
Unit
fVCO
VCO frequency
200
380
MHz
fin
Input frequency
÷2 feedback
100
190
MHz
÷4 feedback
50
95
÷8 feedback
25
47.5
Bypass mode (PLL_EN = 0)
0
200
frefDC
Input duty cycle
25
75
%
VPP
Peak-Peak input voltage
LVPECL
500
1000
mV
VCMR
Common mode range[8]
LVPECL
1.2
VDD – 0.6
V
tr , tf
TCLK input rise/fall time
0.7V to 1.7V
1.0
ns
fMAX
Maximum output frequency
÷2 output
100
190
MHz
÷4 output
50
95
÷8 output
25
47.5
DC
Output duty cycle
fMAX < 100 MHz
47.5
52.5
%
fMAX > 100 MHz
45
55
tr , tf
Output rise/fall times
0.6V to 1.8V
0.1
1.0
ns
t(φ)
Propagation delay (static phase offset) TCLK to FB_IN
–100
100
ps
PCLK to FB_IN
–100
100
tsk(O)
Output-to-Output skew
150
ps
tPLZ, HZ
Output disable time
10
ns
tPZL, ZH
Output enable time
10
ns
BW
PLL closed loop bandwidth (–3dB)
÷2 feedback
2.2
MHz
÷4 feedback
0.85
÷8 feedback
0.6
tJIT(CC)
Cycle-to-Cycle jitter
Same frequency
150
ps
Multiple frequencies
250
tJIT(PER)
Period jitter
Same frequency
100
ps
Multiple frequencies
175
tJIT(φ)
I/O phase jitter
175
ps
tLOCK
Maximum PLL lock time
1
ms
Notes
7. AC characteristics apply for parallel output termination of 50
Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies
within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
[+] Feedback


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