PRELIMINARY
CY14B104KA, CY14B104MA
Document #: 001-07103 Rev. *J
Page 7 of 31
above VSWITCH) the OSCEN bit is checked for “enabled” status.
If the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to “1”. Check for this condition
and then write ‘0’ to clear the flag. Note that in addition to setting
the OSCF flag bit, the time registers are reset to the “Base Time”
(see Setting the Clock on page 6), which is the value last written
to the timekeeping registers. The control or calibration registers
and the OSCEN bit are not affected by the ‘oscillator failed’
condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit
which may have become set when the system was first powered
on.
To reset OSCF, set the write bit “W” (in the flags register at
0x7FFF0) to a “1” to enable writes to the Flag register. Write a
“0” to the OSCF bit and then reset the write bit to “0” to disable
writes.
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal
frequency of 32.768 KHz. Clock accuracy depends on the quality
of the crystal, usually specified to 35 ppm limits at 25°C. This
error could equate to +1.53 minutes per month. The
CY14B104KA employs a calibration circuit that improves the
accuracy to +1 or –2 ppm at 25°C. The calibration circuit adds or
subtracts counts from the oscillator divider circuit.
The number of times pulses are suppressed (subtracted,
negative calibration) or split (added, positive calibration)
depends on the value loaded into the five calibration bits found
in the calibration register at 0x7FFF8. Adding counts speeds the
clock up; subtracting counts slows the clock down. The
calibration bits occupy the five lower order bits in the control
register 8. These bits are set to represent any value between 0
and 31 in binary form. Bit D5 is a sign bit, where ‘1’ indicates
positive calibration and ‘0’ indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes
in the cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator cycles.
If a binary ‘1’ is loaded into the register, only the first 2 minutes
of the 64 minute cycle are modified; if a binary ‘6’ is loaded, the
first 12 are affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles
for every 125,829,120 actual oscillator cycles; that is, 4.068 or
–2.034 ppm of adjustment for every calibration step in the
calibration register.
To determine how to set the calibration, the CAL bit in the flags
register at 0x7FFF0 is set to ‘1’, which causes the INT pin to
toggle at a nominal 512 Hz. Any deviation measured from the
512 Hz indicates the degree and direction of the required
correction. For example, a reading of 512.01024 Hz indicates a
+20 ppm error, which requires the loading of a –10 (001010) into
the calibration register. Note that setting or changing the
calibration register does not affect the frequency test output
frequency.
To set or clear CAL, set the write bit “W” (in the flags register at
0x7FFF0) to “1” to enable writes to the Flag register. Write a
value to CAL, and then reset the write bit to “0” to disable writes.
Alarm
The alarm function compares user programmed values of alarm
time/date (stored in the registers 0x7FFF1-5) with the corre-
sponding time of day/date values. When a match occurs, the
alarm internal flag (AF) is set and an interrupt is generated on
INT pin if Alarm Interrupt Enable (AIE) bit is set. If the interrupt is
triggered at the time when the user is reading the RTC Flags
register, it is not reflected on INT pin until the user completes the
read operation.
There are four alarm match fields: date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required. In this condition, alarm is disabled.
Selecting all match values (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x7FFF0 indicates that a date or time match has occurred. The
AF bit is set to “1” when a match occurs. Reading the flags or
control register clears the alarm flag bit (and all others). A
hardware interrupt pin may also be used to detect an alarm
event.
Note CY14B104KA/CY14B104MA require the alarm match bit
for seconds (0x7FFF2 - D7) to be set to ‘0’ for the proper
operation of Alarm Flag and Interrupt.
Alarm registers are not nonvolatile and therefore, they need to
be reinitialized by software on power up. To set, clear, or enable
an alarm, set the ‘W’ bit (in Flags Register - 0x7FFFF) to “1” to
enable writes to Alarm Registers. After writing the alarm value,
clear the ‘W’ bit back to “0” for the changes to take effect.
Watchdog Timer
The watchdog timer is a free running down counter that uses the
32 Hz clock (31.25 ms) derived from the crystal oscillator. The
oscillator must be running for the watchdog to function. It begins
counting down from the value loaded in the watchdog timer
register.
The counter consists of a loadable register and a free running
counter. On power up, the watchdog timeout value in register
0x7FFF7 is loaded into the counter load register. Counting
begins on power up and restarts from the loadable value any time
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is
compared to the terminal value of 0. If the counter reaches this
value, it causes an internal flag and an optional interrupt output.
The timeout interrupt is prevented by setting WDS bit to ‘1’ before
the counter reaches ‘0’. This causes the counter to reload with
the watchdog timeout value and get restarted. As long as the
WDS bit is set before the counter reaches the terminal value, the
interrupt and flag never occurs.
New timeout values are written by setting the watchdog write
(WDW) bit to ‘0’. When the WDW is ‘0’ (from the previous
operation), new writes to the watchdog timeout value bits D5–D0
enable the modification of timeout values. When WDW is ‘1’,
then writes to bits D5–D0 are ignored. The WDW function
enables setting the WDS bit without concern that the watchdog
timer value is modified. A logical diagram of the watchdog timer
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