5

UCC18500/1/2/3

UCC28500/1/2/3

UCC38500/1/2/3

CAOUT: (current amplifier output) This is the output of a

wide bandwidth op amp that senses line current and

commands the PFC pulse width modulator (PWM) to

force the correct current. This output can swing close to

GND, allowing the PWM to force zero duty cycle when

necessary.

CT: (Oscillator timing capacitor) A capacitor from CT to

GND will set the oscillator frequency according to:

()

f

RT CT

=

•

0 725

.

GND: (ground) All voltages measured with respect to

ground. VCC and VREF should be bypassed directly to

GND with a 0.1

µF or larger ceramic capacitor. The timing

capacitor discharge current also returns to this pin, so

the lead from the oscillator timing capacitor to GND

should be as short and direct as possible.

GT1: (gate drive) The output drive for the PFC stage is a

totem pole MOSFET gate driver on GT1. Use a series

gate resistor of at least 5 ohms to prevent interaction be-

tween the gate impedance and the GT1 output driver that

might cause the GT1 to overshoot excessively. Some

overshoot of the GT1 output is always expected when

driving a capacitive load.

GT2: (gate drive) Same as output GT1 for the second

stage output drive. Limited to 50% maximum duty cycle.

IAC: (input ac current) This input to the analog multiplier

is a current. The multiplier is tailored for very low distor-

only multiplier input which should be used for sensing in-

500

µA.

ISENSE1: (current sense) This is the non-inverting input

to the current amplifier. This input and the inverting input

MOUT remain functional down to and below GND.

ISENSE2: (current sense) A resistor from the source of

the lower FET to ground generates the input signal for

the peak limit control of the second stage. The oscillator

ramp can also be summed into this pin, for slope com-

pensation.

MOUT: (multiplier output and current sense amplifier in-

verting input) The output of the analog multiplier and the

inverting input of the current amplifier are connected to-

gether at MOUT. As the multiplier output is a current, this

is a high impedance input so the amplifier can be config-

ured as a differential amplifier to reject ground noise.

Multiplier output current is given by:

()

I

VAOUT

I

KV

MO

AC

FF

=

−•

•

10

2

.

Connect current loop compensation components be-

tween MOUT and CAOUT.

OVP/ENBL: (over-voltage/enable) A window comparator

input which will disable the PFC output driver if the boost

output is 6.67% above nominal or will disable both the

PFC and second stage output drivers and reset SS2 if

pulled below 1.5V. This input is also used to determine

the active range of the second stage PWM.

PKLMT: (PFC peak current limit) The threshold for peak

limit is 0V. Use a resistor divider from the negative side of

the current sense resistor to VREF to level-shift this sig-

nal to a voltage corresponding to the desired overcurrent

threshold across the current sense resistor.

PWRGND: Ground for totem pole output drivers.

RT: (oscillator charging current) A resistor from RT to

GND is used to program oscillator charging current. A re-

sistor between 10k

Ω and 100kΩ is recommended.

SS2: (soft start for PWM) SS2 is at ground for either en-

able low or OVP/ENBL below the UVLO2 threshold

conditions. When enabled, SS2 will charge an external

capacitor with a current source. This voltage will be used

as the voltage error signal during start-up, enabling the

PWM duty cycle to increase slowly. In the event of a dis-

able command or a

UVLO2 dropout, SS2 will quickly

discharge to disable the PWM.

VAOUT: (voltage amplifier output) This is the output of

the opamp that regulates output voltage. The voltage am-

plifier output is internally limited to approximately 5.5V to

prevent overshoot.

VCC: (positive supply voltage) Connect to a stable

source of at least 20mA between 12V and 17V for nor-

mal operation. Bypass VCC directly to GND to absorb

supply current spikes required to charge external

MOSFET gate capacitances. To prevent inadequate Gate

Drive signals, the output devices will be inhibited unless

VCC exceeds the upper under-voltage lockout threshold

and remains above the lower threshold.

VERR: Voltage amp error signal for the second stage.

The error signal is generated by an external amplifier

which drives this pin.

VFF: (RMS feed forward signal) VFF signal generated at

this pin by mirroring Iac into a single pole external filter.

PIN DESCRIPTIONS