CY22050,
CY220501
Document #: 38-07006 Rev. *G
Page 6 of 10
DC Electrical Characteristics
Parameter[4]
Name
Description
Min
Typ.
Max
Unit
IOH3.3
Output High Current
VOH = VDD – 0.5V, VDD/VDDL = 3.3V
12
24
mA
IOL3.3
Output Low Current
VOL = 0.5V, VDD/VDDL = 3.3V
12
24
mA
IOH2.5
Output High Current
VOH = VDDL – 0.5V, VDDL = 2.5V
8
16
mA
IOL2.5
Output Low Current
VOL = 0.5V, VDDL = 2.5V
8
16
mA
VIH
Input High Voltage
CMOS levels, 70% of VDD
0.7
1.0
VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
00.3
VDD
IVDD
[5,6]
Supply Current
AVDD/VDD Current
45
mA
IVDDL3.3
[5,6]
Supply Current
VDDL Current (VDDL = 3.465V)
25
mA
IVDDL2.5
[5,6]
Supply Current
VDDL Current (VDDL = 2.625V)
17
mA
IDDS
Power Down Current
VDD = VDDL = AVDD = 3.465V
50
μA
IOHZ
IOLZ
Output Leakage
VDD = VDDL = AVDD = 3.465V
10
μA
AC Electrical Characteristics
Parameter[4]
Name
Description
Min
Typ.
Max
Unit
t1
Output frequency,
commercial temp
Clock output limit, 3.3V
0.08 (80 kHz)
200
MHz
Clock output limit, 2.5V
0.08 (80 kHz)
166.6
MHz
Output frequency, indus-
trial temp
Clock output limit, 3.3V
0.08 (80 kHz)
166.6
MHz
Clock output limit, 2.5V
0.08 (80 kHz)
150
MHz
t2
Output duty cycle
Duty cycle is defined in Figure 4; t1/t2
fOUT > 166 MHz, 50% of VDD
40
50
60
%
Duty cycle is defined in Figure 4; t1/t2
fOUT < 166 MHz, 50% of VDD
45
50
55
%
t3LO
Rising edge slew rate
(VDDL = 2.5V)
Output clock rise time, 20% – 80% of VDDL.
Defined in Figure 5
0.6
1.2
V/ns
t4LO
Falling edge slew rate
(VDDL = 2.5V)
Output clock fall time, 80% – 20% of VDDL.
Defined in Figure 5
0.6
1.2
V/ns
t3HI
Rising edge slew rate
(VDDL = 3.3V)
Output clock rise time, 20% – 80% of VDD/VDDL.
Defined in Figure 5
0.8
1.4
V/ns
t4HI
Falling edge slew rate
(VDDL = 3.3V)
Output clock fall time, 80% – 20% of VDD/VDDL.
Defined in Figure 5
0.8
1.4
V/ns
t5[7]
Skew
Output-output skew between related outputs
250
ps
t6[8]
Clock jitter
Peak-to-peak period jitter (see Figure 6)250
ps
t10
PLL lock time
0.30
3
ms
Notes
4. Not 100% tested, guaranteed by design.
5. IVDD currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz. All outputs are
loaded with 15pF.
6. Use CyClocksRT to calculate actual IVDD and IVDDL for specific output frequency configurations.
7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information.
8. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, VDDL (2.5V or 3.3V), temperature,
and output load. For more information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cypress.com,
or contact your local Cypress Field Applications Engineer.
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