PRELIMINARY
CY14B101KA/CY14B101MA
Document #: 001-42880 Rev. *C
Page 2 of 29
Pinouts
Figure 1. Pin Diagram - 44-Pin, 54-Pin TSOP II, and 48-Pin SSOP
Pin Definitions
Pin Name
I/O Type
Description
A0 – A16
Input
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.
A0 – A15
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.
DQ0 – DQ7
Input/Output
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ0 – DQ15
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
NC
No Connect
No Connects. This pin is not connected to the die.
WE
Input
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is
written to the specific address location.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15 - DQ8.
BLE
Input
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.
Xout
Output
Crystal Connection. Drives crystal on start up.
Xin
Input
Crystal Connection. For 32.768 kHz crystal.
VRTCcap
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used.
VRTCbat
Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.
NC
A8
Xin
Xout
VSS
DQ6
DQ5
DQ4
VCC
A13
DQ3
A12
DQ2
DQ1
DQ0
OE
A9
CE
NC
A0
A1
A2
A3
A4
A5
A6
A11
A7
A14
A15
A16
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 - TSOP II
A10
VRTCbat
WE
DQ7
HSB
INT
VSS
VCC
VCAP
VRTCcap
(x8)
NC
DQ7
DQ6
DQ5
DQ4
VCC
DQ3
DQ2
DQ1
DQ0
NC
A0
A1
A2
A3
A4
A5
A6
A7
VCAP
WE
A8
A10
A11
A12
A13
A14
A15
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
54 - TSOP II
OE
CE
VCC
INT
VSS
NC
A9
NC
NC
54
53
52
51
49
50
HSB
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
DQ 11
DQ 10
DQ9
DQ8
(x16)
VRTCcap
VRTCbat
Xin
Xout
[6]
[6]
[7]
[7
NC
A8
Xout
Xin
VSS
DQ6
DQ5
DQ4
VCC
A13
DQ3
A12
DQ2
DQ1
DQ0
OE
A9
CE
NC
A0
A1
A2
A3
A4
A5
A6
A11
A7
A14
A15
A16
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
A10
V
RTCbat
WE
DQ7
HSB
INT
VSS
VCC
VCAP
VRTCcap
45
46
47
48
NC
NC
NC
NC
48 - SSOP
(x8)
[5]
[4]
[4]
[5]
Top View
(not to scale)
(not to scale)
(not to scale)
Top View
Top View
Notes
4. Address expansion for 2 Mbit. NC pin not connected to die.
5. Address expansion for 4 Mbit. NC pin not connected to die.
6. Address expansion for 8 Mbit. NC pin not connected to die.
7. Address expansion for 16 Mbit. NC pin not connected to die.
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