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CY2305, CY2309
Document #: 38-07140 Rev. *J
Page 8 of 15
Typical Duty Cycle[8] and IDD Trends
[9] for CY2305-1 and CY2309-1
Duty Cycle Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
33 MHz
66 MHz
100 MHz
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3
3.1
3.2
3.3
3.4
3.5
3.6
VDD (V)
33 MHz
66 MHz
100 MHz
133 MHz
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20
40
60
80
100
120
140
Fre que ncy (MHz)
-40C
0C
25C
70C
85C
Duty Cycle Vs Frequency
(for 15 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20
40
60
80
100
120
140
Fre que ncy (MHz)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
01234
56789
# of Loaded Outputs
33 MHz
66 MHz
100 MHz
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
01
23
456
78
9
# of Loaded Outputs
33 MHz
66 MHz
100 MHz
Notes
8. Duty cycle is taken from typical chip measured at 1.4V.
9. IDD data is calculated from IDD = ICORE + nCVf, where ICORE is the unloaded current. (n = # of outputs; C = Capacitance load per output (F); V = Supply Voltage (V);
f = frequency (Hz)).
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