CY22393, CY223931, CY22394, CY22395
Document #: 38-07186 Rev. *E
Page 7 of 19
Clk*_FS[2:0]
Each of the four main output clocks (CLKA–CLKD) has a
three-bit code that determines the clock sources for the output
divider. The available clock sources are: Reference, PLL1, PLL2,
and PLL3. Each PLL provides both positive and negative phased
outputs, for a total of seven clock sources (see Table 2). Note
that the phase is a relative measure of the PLL output phases.
No absolute phase relation exists at the outputs.
Xbuf_OE
This bit enables the XBUF output when HIGH. For the CY22395,
Xbuf_OE = 0.
PdnEn
This bit selects the function of the SHUTDOWN/OE pin. When
this bit is HIGH, the pin is an active LOW shutdown control. When
this bit is LOW, this pin is an active HIGH output enable control.
Clk*_ACAdj[1:0]
These bits modify the output predrivers, changing the duty cycle
through the pads. These are nominally set to 01, with a higher
value shifting the duty cycle higher. The performance of the
nominal setting is guaranteed.
Clk*_DCAdj[1:0]
These bits modify the DC drive of the outputs. The performance
of the nominal setting is guaranteed.
PLL*_Q[7:0]
PLL*_P[9:0]
PLL*_P0
These are the 8-bit Q value and 11-bit P values that determine
the PLL frequency. The formula is:
PLL*_LF[2:0]
These bits adjust the loop filter to optimize the stability of the PLL.
Table 4
can
be
used
to
guarantee
stability.
However,
CyClocksRT uses a more complicated algorithm to set the loop
filter for enhanced jitter performance. Use the Print Preview
function in CyClocksRT to determine the charge pump settings
for optimal jitter performance.
PLL*_En
This bit enables the PLL when HIGH. If PLL2 or PLL3 are not
enabled, then any output selecting the disabled PLL must have
a divider setting of zero (off). Since the PLL1_En bit is dynamic,
internal logic automatically turns off dependent outputs when
PLL1_En goes LOW.
DivSel
This bit controls which register is used for the CLKA and CLKB
dividers.
OscCap[5:0]
This controls the internal capacitive load of the oscillator. The
approximate effective crystal load capacitance is:
Set to zero for external reference clock.
Table 2. Clock Source
Clk*_FS[2:0]
Clock Source
000
Reference Clock
001
Reserved
010
PLL1 0
° Phase
011
PLL1 180
° Phase
100
PLL2 0
° Phase
101
PLL2 180
° Phase
110
PLL3 0
° Phase
111
PLL3 180
° Phase
Table 3. Output Drive Strength
Clk*_DCAdj[1:0]
Output Drive Strength
00
–30% of nominal
01
Nominal
10
+15% of nominal
11
+50% of nominal
Table 4. Loop Filter Settings
PLL*_LF[2:0]
PT Min
PT Max
00016231
001
232
626
010
627
834
011
835
1043
100
1044
1600
F
PLL
F
REF
P
T
Q
T
-------
⎝⎠
⎛⎞
×
=
P
T
2P
3
+
()
×
() PO
+
=
Q
T
Q2
+
=
Equation 1
C
LOAD
6pF
OscCap
0.375pF
×
()
+
=
Equation 2
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