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CY14B104M-ZSP25XC Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY14B104M-ZSP25XC Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 33 page CY14B104K, CY14B104M Document #: 001-07103 Rev. *S Page 10 of 33 Flags Register The flags register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. These flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts when a flag is set. These flags are automatically reset when the register is read. The flags register is automatically loaded with the value 0x00 on power-up (except for the OSCF bit. See Stopping and Starting the Oscillator on page 8). Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Recommended Values Y1 = 32.768 kHz (12.5 pF) C1 = 12 pF C2 = 69 pF Note The recommended values for C1 and C2 include board trace capacitance. Xout Xin Y1 C2 C1 WDF - Watchdog Timer Flag WIE - Watchdog Interrupt PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low Enable Watchdog Timer Power Monitor Clock Alarm VINT WDF WIE PF PFE AF AIE P/L Pin Driver H/L INT VCC VSS [+] Feedback [+] Feedback |
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