CY14B256K
256 Kbit (32K x 8) nvSRAM with Real Time Clock
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 001-06431 Rev. *H
Revised February 24, 2009
Features
■ 25 ns, 35 ns, and 45 ns access times
■ Pin compatible with STK17T88
■ Data integrity of Cypress nvSRAM combined with full featured
Real Time Clock
❐ Low power, 350 nA RTC current
❐ Capacitor or battery backup for RTC
■ Watchdog timer
■ Clock alarm with programmable interrupts
■ Hands off automatic STORE on power down with only a small
capacitor
■ STORE to QuantumTrap™ initiated by software, device pin, or
on power down
■ RECALL to SRAM initiated by software or on power up
■ Infinite READ, WRITE, and RECALL cycles
■ High reliability
❐ Endurance to 200K cycles
❐ Data retention: 20 years at 55°C
■ Single 3V operation with tolerance of +20%, -10%
■ Commercial and industrial temperature
■ 48-Pin SSOP (ROHS compliant)
Functional Description
The Cypress CY14B256K combines a 256 Kbit nonvolatile static
RAM with a full-featured real time clock in a monolithic integrated
circuit.
The
embedded
nonvolatile
elements
incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvolatile data resides in
the nonvolatile elements.
The real time clock function provides an accurate clock with leap
year tracking and a programmable high accuracy oscillator. The
alarm function is programmable for one time alarms or periodic
seconds, minutes, hours, or days. There is also a programmable
watchdog timer for process control.
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
STATIC RAM
ARRAY
512 X 512
QuantumTrap
512 X 512
STORE
RECALL
COLUMN IO
COLUMN DEC
OE
CE
WE
HSB
VCC
VCAP
A13
- A0
A0 A1 A2 A3 A4 A10
A5
A6
A7
A8
A9
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RTC
MUX
A14
- A0
x1
x2
INT
VRTCbat
VRTCcap
A11
Logic Block Diagram
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