8 / 27 page
CY8C21345,
CY8C22345, CY8C22545
Document Number: 001-43084 Rev. *H
Page 8 of 27
CY8C22545 44-Pin TQFP
Table 4. Pin Definitions
Pin No.
Type
Pin Name
Description
Digital
Analog
1
IO
ML
P2[5]
Optional ADC External Vref
2
IO
ML
P2[3]
3
IO
ML
P2[1]
4
Power
Vdd
Supply Voltage
5
IO
ML
P4[5]
6
IO
ML
P4[3]
7
IO
ML
P4[1]
8
Power
Vss
Ground Connection
9
IO
ML
P3[7]
10
IO
ML
P3[5]
11
IO
ML
P3[3]
12
IO
ML
P3[1]
13
IO
ML
P1[7]
I2C Serial Clock (SCL)
14
IO
ML
P1[5]
I2C Serial Data (SDA)
15
IO
ML
P1[3]
16
IO
ML
P1[1]*
Crystal (XTALin), I2C Serial
Clock (SCL), TC SCLK
17
Power
Vss
Ground Connection
18
IO
MR
P1[0]*
Crystal (XTALout), I2C Serial
Data (SDA), TC SDATA
19
IO
MR
P1[2]
20
IO
MR
P1[4]
Optional External Clock Input
(EXTCLK)
21
IO
MR
P1[6]
22
IO
MR
P3[0]
23
IO
MR
P3[2]
24
IO
MR
P3[4]
25
IO
MR
P3[6]
26
Input
XRES
Active High Pin Reset with
Internal Pull Down
27
IO
MR
P4[0]
28
IO
MR
P4[2]
29
IO
MR
P4[4]
30
Power
Vss
Ground Connection
31
IO
MR
P2[0]
32
IO
MR
P2[2]
33
IO
MR
P2[4]
34
IO
I, MR
P2[6]
To Compare Column 1
35
IO
I, MR
P0[0]
36
IO
I, MR
P0[2]
37
IO
I, MR
P0[4]
ADC_Ext_Vref, ML, P2[5]
ML, P2[3]
ML, P2[1]
Vdd
TQFP
1
2
3
4
5
6
7
8
24
23
31
30
29
28
27
26
P2[0], MR
XRES
P2[4], MR
11
10
9
25
32
33
ML, P4[5]
ML, P4[3]
ML, P4[1]
ML, P3[7]
ML, P3[5]
ML, P3[3]
P3[2], MR
P3[4], MR
P3[6], MR
P4[0], MR
P4[2], MR
P4[4], MR
Vss
P2[2], MR
Vss
Figure 4. Pin Diagram
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
