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CY7C2568KV18-500BZC Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY7C2568KV18-500BZC
Description  72-Mbit DDR-II SRAM 2-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C2568KV18-500BZC Datasheet(HTML) 6 Page - Cypress Semiconductor

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PRELIMINARY
CY7C2566KV18, CY7C2577KV18
CY7C2568KV18, CY7C2570KV18
Document Number: 001-15889 Rev. *D
Page 6 of 28
Table 2. Pin Definitions
Pin Name
IO
Pin Description
DQ[x:0]
Input Output-
Synchronous
Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q[x:0] are automatically tri-stated.
CY7C2566KV18
− DQ[7:0]
CY7C2577KV18
− DQ[8:0]
CY7C2568KV18
− DQ[17:0]
CY7C2570KV18
− DQ[35:0]
LD
Input-
Synchronous
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
NWS0,
NWS1
Input-
Synchronous
Nibble Write Select 0, 1
− Active LOW (CY7C2566KV18 only). Sampled on the rising edge of the K
and K clocks during write operations. Used to select which nibble is written into the device during the
current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3
− Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C2577KV18
− BWS0 controls D[8:0]
CY7C2568KV18
− BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C2570KV18
− BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (2 arrays each of 4M x 8) for CY7C2566KV18 and 8M x 9 (2 arrays each of 4M x9) for
CY7C2577KV18, 4M x 18 (2 arrays each of 2M x 18) for CY7C2568KV18, and 2M x 36 (2 arrays each
of 1M x 36) for CY7C2570KV18.
R/W
Input-
Synchronous
Synchronous Read or Write input. When LD is LOW, this input designates the access type (read when
R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
ODT [3]
On-Die
Termination
input pin
On-Die Termination Input. This pin is used for On-Die termination of the input signals. ODT range
selection is made during power up initialization. A LOW on this pin selects a low range that follows RQ/3.33
for 175
Ω < RQ < 350Ω (where RQ is the resistor tied to ZQ pin). A HIGH on this pin selects a high range
that follows RQ/1.66 for 175
Ω < RQ < 250Ω (where RQ is the resistor tied to ZQ pin). When left floating,
a high range termination value is selected by default.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0].
Note
3. On-Die Termination (ODT) feature is supported for D[x:0], BWS[x:0], and K/K inputs.
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