CY7C65621/31
Document #: 001-52934 Rev. **
Page 3 of 24
Introduction
EZ-USB HX2LP Lite™ is Cypress’ next generation family of high
performance, low power USB 2.0 hub controllers. HX2LP Lite is
an ultra low power single chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB Serial
Interface Engine (SIE), USB Hub Control and Repeater logic,
and Transaction Translator (TT) logic. Cypress has also
integrated many external passive components such as pull up
and pull down resistors, reducing the overall bill of materials
required to implement a hub design. The HX2LP portfolio
consists of:
1. CY7C65631: 4-port/single transaction translator
This device option is for ultra low power applications that re-
quire four downstream ports. All four ports share a single
transaction translator. The CY7C65631 is available in a 56
QFN and is also pin-for-pin compatible with the CY7C65640.
2. CY7C65621:
This device option is for a 2-port bus powered application.
Both ports share a single transaction translator. The
CY7C65621 is available in a 56 QFN.
All device options are supported by Cypress’ world class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
USB Serial Interface Engine
The Serial Interface Engine (SIE) allows the CY7C65621/31 to
communicate with the USB host. The SIE handles the following
USB activity independently of the Hub Control Block.
■ Bit stuffing/unstuffing
■ Checksum generation/checking
■ TOKEN type identification
■ Address checking.
Hub Repeater
The Hub Repeater manages connectivity between upstream and
downstream facing ports that are operating at the same speed.
It supports full speed, low speed, and high speed connectivity.
According to the USB 2.0 specification, the HUB Repeater
provides the following functions:
■ Sets up and tears down connectivity on packet boundaries
■ Ensures orderly entry into and out of the Suspend state,
including proper handling of remote wakeups.
Transaction Translator
The Transaction Translator (TT) basically translates data from
one speed to another. A TT takes high speed split transactions
and translates them to full or low speed transactions when the
hub is operating at high speed (the upstream port is connected
to a high speed host controller) and has a full or low speed
devices attached. The operating speed of a device attached on
a downstream facing port determines whether the Routing Logic
connects a port to the Transaction Translator or Hub Repeater.
If a full or low speed device is connected to the hub operating at
high speed, the data transfer route includes the Transaction
Translator. If a high speed device is connected to this high speed
hub, the route only includes the repeater and no Transaction
Translator because the device and the hub operate at the same
speed. When the hub is operating at full speed (the upstream
port is connected to a full speed host controller), a high speed
peripheral does not operate at its full capability. These devices
only work at full speed. Full and low speed devices connected to
this hub operate at their normal speed.
Applications
Typical applications for the HX2LP Lite device family are:
■ Standalone hubs
■ Motherboard hubs
■ Monitor hubs
■ Advanced port replicators
■ Docking stations
■ Split-PC designs
■ External personal storage drives
■ Keyboard hubs
Functional Overview
The Cypress CY7C65621/31 USB 2.0 hubs are high perfor-
mance, low system cost solutions for USB. The CY7C65621/31
USB 2.0 hubs integrate 1.5 kΩ upstream pull up resistors for full
speed operation and all downstream 15 kΩ pull down resistors
and series termination resistors on all upstream and downstream
D+ and D– pins. This results in optimization of system costs by
providing built-in support for the USB 2.0 specification.
System Initialization
On power up, the CY7C65621/31 reads an external SPI
EEPROM for configuration information. At the most basic level,
this EEPROM has the Vendor ID (VID), Product ID (PID), and
Device ID (DID) for the customer's application. For more
specialized applications, other configuration options can be
specified. See Configuration Options on page 12 for more
details.
After reading the EEPROM, if VBUSPOWER (connected to
up-stream VBUS) is high, CY7C65621/31 enables the pull up
resistor on D+ to indicate its presence to the upstream hub, after
which a USB Bus Reset is expected. During this reset,
CY7C65621/31 initiates a chirp to indicate that it is a high speed
peripheral. In a USB 2.0 system, the upstream hub responds with
a chirp sequence, and CY7C65621/31 is in a high speed mode,
with the upstream D+ pull up resistor turned off. In USB 1.x
systems, no such chirp sequence from the upstream hub is seen,
and CY7C65621/31 operates as a normal 1.x hub (operating at
full speed).
Enumeration
After a USB Bus Reset, CY7C65621/31 is in an unaddressed,
unconfigured state (configuration value set to ’0’). During the
enumeration process, the host sets the hub's address and
configuration.
When the hub is configured, the full hub functionality is available.
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