3 / 30 page
CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Document Number: 001-07037 Rev. *D
Page 3 of 30
Logic Block Diagram (CY7C1413BV18)
Logic Block Diagram (CY7C1415BV18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
19
72
18
BWS[1:0]
VREF
Write
Reg
36
A(18:0)
19
18
CQ
CQ
DOFF
Q[17:0]
18
18
18
Write
Reg
Write
Reg
Write
Reg
C
C
18
CLK
A(17:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
18
144
36
BWS[3:0]
VREF
Write
Reg
72
A(17:0)
18
36
CQ
CQ
DOFF
Q[35:0]
36
36
36
Write
Reg
Write
Reg
Write
Reg
C
C
36
[+] Feedback