6

UCC1570

UCC2570

UCC3570

Frequency Set

A capacitor from FREQ to GND will determine a constant

clock frequency. Frequency is:

()

F

=

•

18

4

.

If required, frequency can be trimmed down from the

The reduction in frequency is a function of the ratio of

eration.

External synchronization can be accomplished by cou-

pling a narrow pulse to a resistor inserted in series with

R4/200 and the synchronizing pulse width should be less

than 5% of the oscillator period.

External synchronization can also be accomplished by

driving FREQ with an CMOS inverter. The inverter must

be able to sink (4

• I4) with at a voltage less than the

3.5V upper threshold of the oscillator. It must also be

able to source 36

• I4 at a voltage greater than the 1.5V

lower threshold of the oscillator. As long as FREQ is held

high, the output is guaranteed to be low.

Gate Drive Output

The UCC1570 is capable of 1A peak output current. By-

pass VCC with at least 0.1

µF directly to PGND. Use a

capacitor with low equivalent series resistance and in-

ductance. The connection from OUT to the MOSFET

gate should have a 2

Ω or greater damping resistor and

the length should be minimized. A low impedance con-

nection must be established between the MOSFET

source (or the ground side of the current sense resistor),

the VCC bypass capacitor and PGND. PGND should

then be connected by a single path (shown as RGND in

the application) to GND.

APPLICATION INFORMATION (cont.)

CLOCK

FEEDBK

RAMP

OUT

Figure 2. Ramp and PWM waveforms.