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CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Document #: 38-06078 Rev. *B
Page 11 of 18
Notes
29. CE = HIGH for the duration of the above timing (both write and read cycle).
30. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
31. Semaphores are reset (available to both ports) at cycle start.
32. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Switching Waveforms(continued)
tSOP
tSAA
VALID ADRESS
VALID ADRESS
tHD
DATAIN VALID
DATAOUT VALID
tOHA
tAW
tHA
tACE
tSOP
tSCE
tSD
tSA
tPWE
tSWRD
tDOE
WRITE CYCLE
READ CYCLE
OE
R/W
I/O 0
SEM
0–A 2
Figure 9. Semaphore Read After Write Timing, Either Side[29]
A
MATCH
tSPS
A0L–A2L
MATCH
R/WL
SEML
A 0R–A2R
R/WR
SEM R
Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32]
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